Re: [PATCH v4 14/15] spi: cadence-qspi: Add support for the Renesas RZ/N1 controller

[Miquel Raynal]

On 29/01/2026 at 14:44:36 +01, Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:

> Hi Miquèl,
>
> Thanks for your patch!
>
> On Thu, 22 Jan 2026 at 16:14, Miquel Raynal (Schneider Electric)
> <miquel.raynal@xxxxxxxxxxx> wrote:
>> Renesas RZ/N1 QSPI controllers embed a modified version of the Cadence
>> IP with the following settings:
>> - a limited bus clock range
>> - no DTR support
>> - no DMA
>> - no useful interrupt flag
>> - only direct accesses (no INDAC mode)
>> - write protection
>>
>> The controller has been tested by running the SPI NOR check list with a
>> custom RZ/N1D400 based board mounted with a Spansion s25fl128s1 quad
>
> "RZN1D-DB"?

I am indeed talking about the RZ/N1D400 here which is the "nice"
official name of the SoC. The board I was using is a custom board, not
the publicly available DB.

>
>> SPI.
>>
>> Tested-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
>> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@xxxxxxxxxxx>
>
>> --- a/drivers/spi/spi-cadence-quadspi.c
>> +++ b/drivers/spi/spi-cadence-quadspi.c
>> @@ -110,6 +110,7 @@ struct cqspi_st {
>>         bool                    apb_ahb_hazard;
>>
>>         bool                    is_jh7110; /* Flag for StarFive JH7110 SoC */
>> +       bool                    is_rzn1; /* Flag for Renesas RZN1 SoC */
>
> RZ/N1

Crap :-) I will rebase the two patches Mark couldn't apply and add this
typo fix as a follow-up.

Thanks,
Miquèl