Re: [PATCH V3] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup

[Yao Zi]

On Sun, Jan 25, 2026 at 01:39:41AM -0500, guoren@xxxxxxxxxx wrote:
> From: "Guo Ren (Alibaba DAMO Academy)" <guoren@xxxxxxxxxx>
> 
> The early version of XuanTie C910 core has a store merge buffer
> delay problem. The store merge buffer could improve the store queue
> performance by merging multi-store requests, but when there are not
> continued store requests, the prior single store request would be
> waiting in the store queue for a long time. That would cause
> significant problems for communication between multi-cores. This
> problem was found on sg2042 & th1520 platforms with the qspinlock
> lock torture test.
> 
> So appending a fence w.o could immediately flush the store merge
> buffer and let other cores see the write result.
> 
> This will apply the WRITE_ONCE errata to handle the non-standard
> behavior via appending a fence w.o instruction for WRITE_ONCE().
> 
> This problem is only observed on the sg2042 hardware platform by
> running the lock_torture test program for half an hour. The problem
> was not found in the user space application, because interrupt can
> break the livelock.
> 
> Reviewed-by: Leonardo Bras <leobras@xxxxxxxxxx>
> Tested-by: Han Gao <gaohan@xxxxxxxxxxx>
> Cc: Yao Zi <me@xxxxxxxx>
> Cc: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx>
> Cc: Paul Walmsley <pjw@xxxxxxxxxx>
> Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@xxxxxxxxxx>

With the patch, I've run heavy multi-core compilation load on SG2042 for
more than 12 hours, and observed no stability issues.

Tested-by: Yao Zi <me@xxxxxxxx>

Thanks,
Yao Zi