Re: [PATCH v2] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable PME status

[Lukas Wunner]

On Wed, Feb 18, 2026 at 06:33:15PM +0100, Rafael J. Wysocki wrote:
> First, keeping the ports in D0 may gate runtime PC10.  Does it not?

The Root Port in question is on the PCH.  I'm not sure, does keeping a
PCH Root Port in D0 also prevent PC10 entry or is that only the case
for Root Ports on the CPU die/tile?

If this does cause a power regression, the pme_is_broken() approach
suggested upthread might be a viable alternative.  It'll allow the
Root Port to go to D3hot but will keep interrupts enabled in the
Slot Control register.

Thanks,

Lukas