Re: [PATCH v2] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable PME status

[Rafael J. Wysocki]

On Thu, Feb 19, 2026 at 9:04 AM Lukas Wunner <lukas@xxxxxxxxx> wrote:
>
> On Wed, Feb 18, 2026 at 06:33:15PM +0100, Rafael J. Wysocki wrote:
> > First, keeping the ports in D0 may gate runtime PC10.  Does it not?
>
> The Root Port in question is on the PCH.  I'm not sure, does keeping a
> PCH Root Port in D0 also prevent PC10 entry or is that only the case
> for Root Ports on the CPU die/tile?

If it is located in the PCH, it should not gate PC10 if in D0 at least
in theory, but it would be good to verify that.

Of course, it will still gate S0ix entry through runtime idle, but
that's a bit moot if the platform is unable to enter S0ix through
runtime idle anyway for other reasons (which is quite likely), or if
the power difference between S0ix and PC10 is small.

> If this does cause a power regression, the pme_is_broken() approach
> suggested upthread might be a viable alternative.  It'll allow the
> Root Port to go to D3hot but will keep interrupts enabled in the
> Slot Control register.

Sounds reasonable to me.