Re: [PATCH v2 2/3] arm64: dts: qcom: sm8550: add OSM L3 node and cpu interconnect nodes

[Konrad Dybcio]

On 2/18/26 7:16 PM, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@xxxxxxxxx>
> 
> Add the OSC L3 Cache controller node.
> 
> Also add the interconnect entry for each cpu, with 3 different paths:
> - CPU to Last Level Cache Controller (LLCC)
> - Last Level Cache Controller (LLCC) to DDR
> - L3 Cache from CPU to DDR interface
> 
> Signed-off-by: Aaron Kling <webgeek1234@xxxxxxxxx>
> ---

This should still be squashed with patch 3, as while you wire up the
CPUs as interconnect consumers, they cast no vote, leading to the
situation Krzysztof mentioned where the performance actually majorly
goes *down*, since the icc core sees no users present and assumes it can
send a zero-vote (which probably translates to F_MIN for the cache)

Konrad