Re: [PATCH v3 15/21] sched/cache: Disable cache aware scheduling for processes with high thread counts

[Peter Zijlstra]

On Wed, Feb 18, 2026 at 11:24:05PM +0530, Madadi Vineeth Reddy wrote:
> Is there a way to make this useful for architectures with small LLC
> sizes? One possible approach we were exploring is to have LLC at a
> hemisphere level that comprise multiple SMT4 cores.

Is this hemisphere an actual physical cache level, or would that be
artificial?