RE: [EXTERNAL] Re: [PATCH RESEND net v1 1/2] octeon_ep: avoid compiler and IQ/OQ reordering
From: Vimlesh Kumar
Date: Fri Feb 20 2026 - 04:06:43 EST
> -----Original Message-----
> From: Paolo Abeni <pabeni@xxxxxxxxxx>
> Sent: Tuesday, February 17, 2026 3:27 PM
> To: Vimlesh Kumar <vimleshk@xxxxxxxxxxx>; netdev@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx
> Cc: Sathesh B Edara <sedara@xxxxxxxxxxx>; Shinas Rasheed
> <srasheed@xxxxxxxxxxx>; Haseeb Gani <hgani@xxxxxxxxxxx>;
> Veerasenareddy Burru <vburru@xxxxxxxxxxx>; Andrew Lunn
> <andrew+netdev@xxxxxxx>; David S. Miller <davem@xxxxxxxxxxxxx>; Eric
> Dumazet <edumazet@xxxxxxxxxx>; Jakub Kicinski <kuba@xxxxxxxxxx>;
> Satananda Burla <sburla@xxxxxxxxxxx>; Abhijit Ayarekar
> <aayarekar@xxxxxxxxxxx>
> Subject: [EXTERNAL] Re: [PATCH RESEND net v1 1/2] octeon_ep: avoid
> compiler and IQ/OQ reordering
>
> On 2/12/26 1: 16 PM, Vimlesh Kumar wrote: > Utilize READ_ONCE and
> WRITE_ONCE APIs for IO queue Tx/Rx > variable access to prevent compiler
> optimization and reordering. You must include into the commit message a
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> On 2/12/26 1:16 PM, Vimlesh Kumar wrote:
> > Utilize READ_ONCE and WRITE_ONCE APIs for IO queue Tx/Rx variable
> > access to prevent compiler optimization and reordering.
>
> You must include into the commit message a more detalied description of
> what could possibly go wrong and way. Also why wmb/rmb are not enough?
>
> AFAICS this is the only driver requiring such annotations to cooperate with
> the H/W and/or the firmware.
Hi Paolo,
Thank you for the review and feedback, we will add more detailed description about using READ_ONCE/WRITE_ONCE API in commit message.
To add more to the explanation:
The compiler could reorder reads/writes to pkts_pending, last_pkt_count, etc., causing stale values to be used when calculating packets to process or register updates to send to hardware. The Octeon hardware requires a read-back after writing to OUT_CNT/IN_CNT registers to ensure the write has been flushed through any posted write buffers before the interrupt resend bit is set. Without this, we have observed cases where the hardware didn't properly update its internal state.
wmb/rmb only provides ordering guarantees but doesn't prevent the compiler from performing optimizations like caching in registers, load tearing etc.
>
> > Additionally, ensure IO queue OUT/IN_CNT registers are flushed by
> > performing a read-back after writing.
> >
> > Relocate IQ/OQ IN/OUT_CNTS updates to occur before NAPI completion,
> > and replace napi_complete with napi_complete_done.
>
> This looks like a separate change, and again requires a more complete
> explaination of what could possibly go wrong and why.
Yes, it looks like a separate fix in retrospect.
Moving the IQ/OQ counter updates before napi_complete_done ensures:
- Counter registers are updated before re-enabling interrupts.
- Prevents a race where new packets arrive but counters aren't properly synchronized.
- napi_complete_done (vs napi_complete) allows for better interrupt coalescing.
I'll split this into two separate patches and provide more detailed commit messages.
>
> /P