Re: [PATCH] drm/msm/dsi: fix hdisplay calculation when programming dsi registers

[Dmitry Baryshkov]

On Tue, Feb 24, 2026 at 02:34:28PM +0800, Pengyu Luo wrote:
> On Tue, Feb 24, 2026 at 7:35 AM Dmitry Baryshkov
> <dmitry.baryshkov@xxxxxxxxxxxxxxxx> wrote:
> >
> > On Sat, Feb 14, 2026 at 06:51:28PM +0800, Pengyu Luo wrote:
> > > Recently, the hdisplay calculation is working for 3:1 compressed ratio
> > > only. If we have a video panel with DSC BPP = 8, and BPC = 10, we still
> > > use the default bits_per_pclk = 24, then we get the wrong hdisplay. We
> > > can draw the conclusion by cross-comparing the calculation with the
> > > calculation in dsi_adjust_pclk_for_compression().
> > >
> > > Since CMD mode does not use this, we can remove
> > > !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) safely.
> > >
> > > Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI")
> > > Signed-off-by: Pengyu Luo <mitltlatltl@xxxxxxxxx>
> > > ---
> > >  drivers/gpu/drm/msm/dsi/dsi_host.c | 14 ++++++++------
> > >  1 file changed, 8 insertions(+), 6 deletions(-)
> > >
> > Could you please point out, which platform / device are you using to
> > test this code?
> >
> Hi, Dmitry.
> 
> I was using Lenovo Yoga Tab Plus(sm8650), it is equipped with a
> native 10-bit panel, the resolution is 2944 x 1840.
> 
> I am using Lenovo Legion Y700 Gen4(sm8750), it is equipped with a
> native 10-bit panel too, the resolution is 1904 x 3040.
> 
> I witnessed that the DSI_ACTIVE_H_END bits in REG_DSI_ACTIVE_H are wrong.
> For Y700 (panel in 8 dsc bpp and 10 bpc mode)
> Upstream: 0x015e0020
> 0x015e - 0x0020 = 318 = DIV_ROUND_UP(1904 / 2 * 8,  24)
> Downstream: 0x011e0020
> 0x011e - 0x0020 = 254 = DIV_ROUND_UP(1904 / 2 * 8,  30)
> 
> dsi_adjust_pclk_for_compression() did:
> new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc),
>                             dsc->bits_per_component * 3);
> new_hdisplay will be halved later for bonded dsi.

Ack, thanks.


Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>



> 
> Original calculation must be wrong, though it is unused. We can refer
> to the downstream too.
> 
> Addition: To support 10-bit for dsi, more fixes are required. e.g.
> programming VID_DST_FORMAT_RGB101010 into REG_DSI_VID_CFG0
> adding MIPI_DSI_FMT_RGB101010 and bpp conversion into drm mipi dsi
> fixing DSC RC parameters? Recently DRM_DSC_1_1_PRE_SCR is hardcoded
> etc.
> 
> I just brought up the panel in 8 dsc bpp and 8 bpc mode. I will try
> 8 dsc bpp and 10 bpc mode after a while.
> 
> Best wishes,
> Pengyu

-- 
With best wishes
Dmitry