[PATCH] Docs: iio: ad7191: Correct clock configuration

[Ammar Mustafa]

Correct the ad7191 documentation to match the datasheet:
- Fix inverted CLKSEL pin logic: device should use external clock when low,
  internal CMOS/crystal when high.
- Correct CMOS-compatible clock pin from MCLK2 to MCLK1.

Signed-off-by: Ammar Mustafa <ammarmustafa34@xxxxxxxxx>
---
 Documentation/iio/ad7191.rst | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Documentation/iio/ad7191.rst b/Documentation/iio/ad7191.rst
index 977d4fea14b0..bb8a1efcfb98 100644
--- a/Documentation/iio/ad7191.rst
+++ b/Documentation/iio/ad7191.rst
@@ -63,12 +63,12 @@ Clock Configuration
 
 The AD7191 supports both internal and external clock sources:
 
-- When CLKSEL pin is tied LOW: Uses internal 4.92MHz clock (no clock property
-  needed)
-- When CLKSEL pin is tied HIGH: Requires external clock source
+- When CLKSEL pin is tied LOW: Requires external clock source
   - Can be a crystal between MCLK1 and MCLK2 pins
-  - Or a CMOS-compatible clock driving MCLK2 pin
+  - Or a CMOS-compatible clock driving MCLK1 pin and MCLK2 left unconnected
   - Must specify the "clocks" property in device tree when using external clock
+- When CLKSEL pin is tied HIGH: Uses internal 4.92MHz clock (no clock property
+  needed)
 
 SPI Interface Requirements
 --------------------------
-- 
2.43.0