Re: [PATCH v8 10/18] arm64: dts: qcom: x1e80100: Add MIPI CSI PHY nodes

[Christopher Obbard]

Hi Bryan,

On Wed, 2026-02-25 at 15:11 +0000, Bryan O'Donoghue wrote:
> Add csiphy nodes for
> 
> - csiphy0
> - csiphy1
> - csiphy2
> - csiphy4
> 
> The irregular naming of the PHYs comes directly from the hardware which for
> whatever reason skipped csiphy3.
> 
> Separating the nodes from CAMSS as we have done with the sensor I2C bus aka
> the CCI interface is justified since the CSIPHYs have their own pinouts and
> voltage rails.
> 
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
> ---

Reviewed-by: Christopher Obbard <christopher.obbard@xxxxxxxxxx>
Tested-by: Christopher Obbard <christopher.obbard@xxxxxxxxxx>

>  arch/arm64/boot/dts/qcom/hamoa.dtsi | 115 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 115 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> index 38f9da6ad9ca5..9c5ebe1b48ecd 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> @@ -707,6 +707,25 @@ smem_mem: smem@ffe00000 {
>  		};
>  	};
>  
> +	csiphy_opp_table: opp-table-csiphy {
> +		compatible = "operating-points-v2";
> +
> +		opp-300000000 {
> +			opp-hz = /bits/ 64 <300000000>;
> +			required-opps = <&rpmhpd_opp_low_svs_d1>;
> +		};
> +
> +		opp-400000000 {
> +			opp-hz = /bits/ 64 <400000000>;
> +			required-opps = <&rpmhpd_opp_low_svs>;
> +		};
> +
> +		opp-480000000 {
> +			opp-hz = /bits/ 64 <480000000>;
> +			required-opps = <&rpmhpd_opp_low_svs>;
> +		};
> +	};
> +
>  	qup_opp_table_100mhz: opp-table-qup100mhz {
>  		compatible = "operating-points-v2";
>  
> @@ -5543,6 +5562,102 @@ cci1_i2c1: i2c-bus@1 {
>  			};
>  		};
>  
> +		csiphy0: csiphy@ace4000 {
> +			compatible = "qcom,x1e80100-csi2-phy";
> +			reg = <0 0x0ace4000 0 0x2000>;
> +
> +			clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
> +				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> +				 <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> +				 <&camcc CAM_CC_CPAS_AHB_CLK>;
> +			clock-names = "csiphy",
> +				      "csiphy_timer",
> +				      "camnoc_axi",
> +				      "cpas_ahb";
> +
> +			operating-points-v2 = <&csiphy_opp_table>;
> +
> +			interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
> +
> +			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> +			#phy-cells = <1>;
> +
> +			status = "disabled";
> +		};
> +
> +		csiphy1: csiphy@ace6000 {
> +			compatible = "qcom,x1e80100-csi2-phy";
> +			reg = <0 0x0ace6000 0 0x2000>;
> +
> +			clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
> +				 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> +				 <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> +				 <&camcc CAM_CC_CPAS_AHB_CLK>;
> +			clock-names = "csiphy",
> +				      "csiphy_timer",
> +				      "camnoc_axi",
> +				      "cpas_ahb";
> +
> +			operating-points-v2 = <&csiphy_opp_table>;
> +
> +			interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
> +
> +			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> +			#phy-cells = <1>;
> +
> +			status = "disabled";
> +		};
> +
> +		csiphy2: csiphy@ace8000 {
> +			compatible = "qcom,x1e80100-csi2-phy";
> +			reg = <0 0x0ace8000 0 0x2000>;
> +
> +			clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
> +				 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> +				 <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> +				 <&camcc CAM_CC_CPAS_AHB_CLK>;
> +			clock-names = "csiphy",
> +				      "csiphy_timer",
> +				      "camnoc_axi",
> +				      "cpas_ahb";
> +
> +			operating-points-v2 = <&csiphy_opp_table>;
> +
> +			interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
> +
> +			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> +			#phy-cells = <1>;
> +
> +			status = "disabled";
> +		};
> +
> +		csiphy4: csiphy@acec000 {
> +			compatible = "qcom,x1e80100-csi2-phy";
> +			reg = <0 0x0acec000 0 0x2000>;
> +
> +			clocks = <&camcc CAM_CC_CSIPHY4_CLK>,
> +				 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
> +				 <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> +				 <&camcc CAM_CC_CPAS_AHB_CLK>;
> +			clock-names = "csiphy",
> +				      "csiphy_timer",
> +				      "camnoc_axi",
> +				      "cpas_ahb";
> +
> +			operating-points-v2 = <&csiphy_opp_table>;
> +
> +			interrupts = <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>;
> +
> +			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> +			#phy-cells = <1>;
> +
> +			status = "disabled";
> +		};
> +
>  		camcc: clock-controller@ade0000 {
>  			compatible = "qcom,x1e80100-camcc";
>  			reg = <0 0x0ade0000 0 0x20000>;