[PATCH v1 06/13] dt-bindings: clock: Add peripheral-1 domain PLL clock
From: Changhuang Liang
Date: Fri Apr 03 2026 - 01:53:17 EST
Add peripheral-1 domain PLL clock for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
---
.../devicetree/bindings/clock/starfive,jhb100-pll.yaml | 1 +
include/dt-bindings/clock/starfive,jhb100-crg.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
index 920fde5e1b0a..1f619adb30a1 100644
--- a/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
@@ -19,6 +19,7 @@ properties:
enum:
- starfive,jhb100-sys0-pll
- starfive,jhb100-per0-pll
+ - starfive,jhb100-per1-pll
clocks:
maxItems: 1
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 55e91ede977e..49fb1694bc79 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -17,6 +17,9 @@
/* PER0PLL clocks */
#define JHB100_PER0PLL_PLL6_OUT 0
+/* PER1PLL clocks */
+#define JHB100_PER1PLL_PLL7_OUT 0
+
/* SYS0CRG clocks */
#define JHB100_SYS0CLK_BMCPCIERP_600 17
#define JHB100_SYS0CLK_BMCPCIERP_100 18
--
2.25.1