Re: [PATCH v1 02/13] dt-bindings: clock: Add system-0 domain PLL clock

[Krzysztof Kozlowski]

On Thu, Apr 02, 2026 at 10:49:34PM -0700, Changhuang Liang wrote:
> Add system-0 domain PLL clock for StarFive JHB100 SoC.
> 
> Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
> ---
>  .../bindings/clock/starfive,jhb100-pll.yaml   | 44 +++++++++++++++++++
>  .../dt-bindings/clock/starfive,jhb100-crg.h   |  6 +++

You did not test your code. Apply patch #1 and test it. Do you see
build-level errors?

Best regards,
Krzysztof