RE: [PATCH v3 0/3] Improvements on RZ/G2L MIPI DSI driver

[Biju Das]

Hi,

> -----Original Message-----
> From: Biju <biju.das.au@xxxxxxxxx>
> Sent: 30 March 2026 11:45
> Subject: [PATCH v3 0/3] Improvements on RZ/G2L MIPI DSI driver
> 
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> Hi All,
> 
> Enhance the RZ/G2L MIPI DSI driver based on section "34.4.2.1 Reset" of the RZ/G2L hardware manual
> Rev.1.50 May 2025. According to this section, it is required to wait >= 1 msec after deasserting the
> CMN_RSTB signal, and writing to DSI PHY timing registers and LINK registers should be done before
> deasserting CMN_RSTB.
> Additionally, the hardware manual suggests display timing settings should be done after the HS clock is
> started.
> 
> v2->v3:
>  * Merged patch#2 and patch#3 to avoid breakage.
>  * Moved the patch from patch#4 to patch#2.
>  * Added fixes tag for patch#2.
>  * Updated commit description for patch#2 and patch#3.
> v1->v2:
>  * Updated commit header and description
>  * Moved the code from rzg2l_mipi_dsi_dphy_init() to rzg2l_mipi_dsi_startup()
>  * Moved the check before calling reset_control_deassert(), so that it will be
>    skipped for RZ/V2H SoC
>  * Added fixes patch for moving rzg2l_mipi_dsi_set_display_timing()
>  * Added fixes patch for assert of CMN_RSTB signal
> 
> Biju Das (3):
>   drm: renesas: rzg2l_mipi_dsi: Move rzg2l_mipi_dsi_set_display_timing()
>   drm: renesas: rzg2l_mipi_dsi: Increase reset deassertion delay
>   drm: renesas: rzg2l_mipi_dsi: Fix deassert/assert of CMN_RSTB signal
> 
>  .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c    | 34 +++++++++++--------
>  1 file changed, 19 insertions(+), 15 deletions(-)
> 

Applied to drm-misc-next.

Cheers,
Biju