Re: [PATCH] ASoC: dt-bindings: cdns: Convert xtfpga I2S to dt-schema

[Max Filippov]

On Thu, Apr 16, 2026 at 8:25 AM Chaitanya Sabnis
<chaitanya.msabnis@xxxxxxxxx> wrote:
>
> Convert the Cadence XTensa FPGA I2S controller plain-text binding
> documentation to standard dt-schema (YAML).
>
> The hardware requires exactly one memory region, one interrupt line,
> and one phandle to the master clock. Verified these constraints against
> the driver source in sound/soc/xtensa/xtfpga-i2s.c.
>
> Signed-off-by: Chaitanya Sabnis <chaitanya.msabnis@xxxxxxxxx>
> ---
>  .../bindings/sound/cdns,xtfpga-i2s.txt        | 18 -------
>  .../bindings/sound/cdns,xtfpga-i2s.yaml       | 48 +++++++++++++++++++
>  2 files changed, 48 insertions(+), 18 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
>  create mode 100644 Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml
>
> diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
> deleted file mode 100644
> index 860fc0da39c0..000000000000
> --- a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -Bindings for I2S controller built into xtfpga Xtensa bitstreams.
> -
> -Required properties:
> -- compatible: shall be "cdns,xtfpga-i2s".
> -- reg: memory region (address and length) with device registers.
> -- interrupts: interrupt for the device.
> -- clocks: phandle to the clk used as master clock. I2S bus clock
> -  is derived from it.
> -
> -Examples:
> -
> -       i2s0: xtfpga-i2s@d080000 {
> -               #sound-dai-cells = <0>;
> -               compatible = "cdns,xtfpga-i2s";
> -               reg = <0x0d080000 0x40>;
> -               interrupts = <2 1>;
> -               clocks = <&cdce706 4>;
> -       };
> diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml
> new file mode 100644
> index 000000000000..9a4a9db3c159
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml
> @@ -0,0 +1,48 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/cdns,xtfpga-i2s.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cadence XTensa FPGA I2S Controller

When put like this it looks like an official name, but it's not and it misses an
important bit: 'xtfpga' is a group name for very specific FPGAs bitstreams
generated for xtensa cores, spelling it as XTensa FPGA makes it less
obvious what it is. I'd suggest keeping the original description.

For other changes:
Reviewed-by: Max Filippov <jcmvbkbc@xxxxxxxxx>

> +
> +maintainers:
> +  - Max Filippov <jcmvbkbc@xxxxxxxxx>
> +
> +allOf:
> +  - $ref: dai-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: cdns,xtfpga-i2s
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +    description: phandle to the clk used as master clock. I2S bus clock is derived from it.
> +
> +  "#sound-dai-cells":
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    i2s@d080000 {
> +        compatible = "cdns,xtfpga-i2s";
> +        reg = <0x0d080000 0x40>;
> +        interrupts = <2 1>;
> +        clocks = <&cdce706 4>;
> +        #sound-dai-cells = <0>;
> +    };
> --
> 2.43.0
>


-- 
Thanks.
-- Max