Re: [PATCH v3 6/6] riscv: dts: microchip: add pinctrl nodes for mpfs/icicle kit

[Conor Dooley]

On Mon, Jan 19, 2026 at 11:03:57AM +0000, Conor Dooley wrote:

> +
> +&i2c0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c0_fabric>;
> +};
> +
> +&i2c1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c1_fabric>;
> +};

Seemingly, I have run into an erratum here. What I noticed that this
didn't match the schematic and changed it when I applied. Turns out,
this is actually correct on engineering sample silicon but not on
production. Something like
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 2d14e92f068d5..9078e5b1e49c1 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -101,16 +101,6 @@ &ccc_nw {
  status = "okay";
};

-&i2c0 {
-  pinctrl-names = "default";
-  pinctrl-0 = <&i2c0_fabric>;
-};
-
-&i2c1 {
-  pinctrl-names = "default";
-  pinctrl-0 = <&i2c1_mssio>;
-};
-
&mmuart1 {
  pinctrl-names = "default";
  pinctrl-0 = <&uart1_fabric>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
index 8afedece89d1f..636493f6584d2 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
@@ -14,6 +14,16 @@ / {
         "microchip,mpfs";
};

+&i2c0 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&i2c0_fabric>;
+};
+
+&i2c1 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&i2c1_mssio>;
+};
+
&syscontroller {
  microchip,bitstream-flash = <&sys_ctrl_flash>;
};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 556aa9638282e..6fadce815c9a2 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -11,3 +11,22 @@ / {
         "microchip,mpfs-icicle-kit",
         "microchip,mpfs";
};
+
+&i2c0 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&i2c0_fabric>;
+};
+
+/*
+ * Due to silicon errata, routing via MSS IOs doesn't work on ES devices.
+ * Instead, i2c1, appearing on B1/C1, which are normally MSS IOs, is routed
+ * via the fabric and back to B1/C1 via "fabric-test" functionality.
+ * This is done silently by Libero, so the iomux0 setting for i2c1 has to
+ * be fabric IO, despite tooling etc saying that MSS IOs are used.
+ *
+ * See Section 3.3 of https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/Errata/polarfiresoc/microsemi_polarfire_soc_fpga_egineering_samples_errata_er0219_v1.pdf
+ */
+&i2c1 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&i2c1_fabric>;
+};

is needed to restore functionality and a further change is required to
"document" in code the extent of the hack required to make it work.

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