[PATCH 10/10] serial: max310x: add comments for PLL limits

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@xxxxxxxxxxxx>

Add comments to help clarify the provenance of the various hardcoded values
used in computing the ref clk.

Assisted-by: Gemini:Pro
Signed-off-by: Hugo Villeneuve <hvilleneuve@xxxxxxxxxxxx>
---
 drivers/tty/serial/max310x.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c
index 748306d1a9329694e90ec4f096dd00e39d457fda..9f423b3b4201d0db07bbd7b15934db36249e7620 100644
--- a/drivers/tty/serial/max310x.c
+++ b/drivers/tty/serial/max310x.c
@@ -585,6 +585,23 @@ static u8 max310x_pll_mult_to_id(u8 pll_mult)
 	}
 }
 
+/*
+ * From table 7 in datasheet: PLLFactor Selector Guide
+ *
+ * +-----------+----------------+-------------------+-------------------+
+ * | PLLFactor | MULTIPLICATION |      fPLLIN       |       fREF        |
+ * |  (1 & 0)  |     FACTOR     +---------+---------+---------+---------+
+ * |           |                |   MIN   |   MAX   |   MIN   |   MAX   |
+ * +-----------+----------------+---------+---------+---------+---------+
+ * |     0     |        6       |  500kHz |  800kHz |   3MHz  |  4.8MHz |
+ * +-----------+----------------+---------+---------+---------+---------+
+ * |     1     |       48       |  850kHz |  1.2MHz | 40.8MHz |  56MHz  |
+ * +-----------+----------------+---------+---------+---------+---------+
+ * |     2     |       96       |  425kHz |   1MHz  | 40.8MHz |  96MHz  |
+ * +-----------+----------------+---------+---------+---------+---------+
+ * |     3     |      144       |  390kHz |  667kHz |  56MHz  |  96MHz  |
+ * +-----------+----------------+---------+---------+---------+---------+
+ */
 static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
 			       unsigned int freq, unsigned int *fref, bool xtal)
 {

-- 
2.47.3