Re: [PATCH v2 2/2] clk: divider: Add some kunit test suites

[Lad, Prabhakar]

Hi Brian,

On Fri, Apr 17, 2026 at 2:21 PM Brian Masney <bmasney@xxxxxxxxxx> wrote:
>
> Hi Lad,
>
> On Thu, Apr 16, 2026 at 5:35 PM Brian Masney <bmasney@xxxxxxxxxx> wrote:
> > On Mon, Apr 13, 2026 at 01:49:12PM +0100, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > +     /*
> > > +      * ULONG_MAX is the canonical way to probe the maximum rate a clock
> > > +      * can produce. With a parent at 1 GHz and the smallest table divider
> > > +      * being 2, the expected maximum is 500 MHz.
> > > +      *
> > > +      * Before the fix this returned 125 MHz (PARENT_RATE / 8), the
> > > +      * minimum rate, because the search loop was bypassed entirely.
> >
> > The "Before the fix" comment should go in the commit log. The comment in
> > the code should describe how the code is right now.
>
> To demonstrate the existing issue, you could structure your series by:
>
> - Introduce the test as the first patch and have it show the issue and
> the current behavior.
> - Put the divider fix in, and update the test for the new behavior.
>
Sure to confirm,

patch #1,  have KUNIT_EXPECT_EQ() with a false positive.
Patch #2: Clock divider fix + updated KUNIT_EXPECT_EQ() with correct
expected values.

Cheers,
Prabhakar