Re: [PATCH 08/10] ARM: dts: qcom: msm8960: add SMSM & SPS

From: Antony Kurniawan Soemardi

Date: Sun Apr 19 2026 - 09:41:40 EST


On 4/18/2026 11:53 PM, Dmitry Baryshkov wrote:
On Tue, Apr 14, 2026 at 01:55:35AM +0700, Antony Kurniawan Soemardi via B4 Relay wrote:
From: Antony Kurniawan Soemardi <linux@xxxxxxxxxxxxxx>

Add the Shared Memory State Machine node to coordinate state transitions
between the Applications processor and the Riva subsystem.

Tested-by: Rudraksha Gupta <guptarud@xxxxxxxxx>
Signed-off-by: Antony Kurniawan Soemardi <linux@xxxxxxxxxxxxxx>
---
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index 218cf3158dfb..107c5613aa4a 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -109,6 +109,31 @@ smem {
hwlocks = <&sfpb_mutex 3>;
};
+ smsm {
+ compatible = "qcom,smsm";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ipc-1 = <&l2cc 8 4>;
+ qcom,ipc-2 = <&l2cc 8 14>;
+ qcom,ipc-3 = <&l2cc 8 23>;
+ qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
+
+ apps_smsm: apps@0 {
+ reg = <0>;
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcnss_smsm: wcnss@3 {
+ reg = <3>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };

Are there other SMSMs (modem, Q6, DSPS)? If so and if you are going to
send another revision, could you please add those?
Yes there are. But I've intentionally left them out for now since
they're unrelated to this Wi-Fi enablement series and I currently have
no way to test them without bringing up the modem, audio, and/or video
subsystems first.

I think it's cleaner to keep this series focused on what's verifiable
today and handle the rest in a future separate series. What do you
think?

--
Thanks,
Antony K. S.