Re: [PATCH v3 5/5] arch: arm64: dts: qcom: Add support for PCIe3a

[Qiang Yu]

On Thu, Apr 16, 2026 at 08:19:09AM +0200, Krzysztof Kozlowski wrote:
> On 16/04/2026 05:24, Qiang Yu wrote:
> > On Wed, Apr 15, 2026 at 09:44:15AM +0200, Krzysztof Kozlowski wrote:
> >> On Sun, Apr 12, 2026 at 11:26:00PM -0700, Qiang Yu wrote:
> >>> Describe PCIe3a controller and PHY. Also add required system resources
> >>> like regulators, clocks, interrupts and registers configuration for PCIe3a.
> >>>
> >>> Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> >>
> >> subject: drop arch.
> >>
> >> Please use subject prefixes matching the subsystem. You can get them for
> >> example with 'git log --oneline -- DIRECTORY_OR_FILE' on the directory
> >> your patch is touching. For bindings, the preferred subjects are
> >> explained here:
> >> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
> >>
> > 
> > Thanks for pointing me the link. I’ll drop arch: in next version.
> > 
> >>> ---
> >>>  arch/arm64/boot/dts/qcom/glymur.dtsi | 316 ++++++++++++++++++++++++++++++++++-
> >>>  1 file changed, 315 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> >>> index f23cf81ddb77a4138deeb4e00dd8b316930a2feb..c15f87c37ecbad72076a6c731f4959a1a8bd8425 100644
> >>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> >>> @@ -736,7 +736,7 @@ gcc: clock-controller@100000 {
> >>>  				 <0>,				/* USB 2 Phy PCIE PIPEGMUX */
> >>>  				 <0>,				/* USB 2 Phy PIPEGMUX */
> >>>  				 <0>,				/* USB 2 Phy SYS PCIE PIPEGMUX */
> >>> -				 <0>,				/* PCIe 3a */
> >>> +				 <&pcie3a_phy>,			/* PCIe 3a */
> >>>  				 <&pcie3b_phy>,			/* PCIe 3b */
> >>>  				 <&pcie4_phy>,			/* PCIe 4 */
> >>>  				 <&pcie5_phy>,			/* PCIe 5 */
> >>> @@ -3640,6 +3640,320 @@ pcie3b_port0: pcie@0 {
> >>>  			};
> >>
> >> ...
> >>
> >>>> +		pcie3a_phy: phy@f00000 {
> >>
> >> Same comment as before.
> >>
> > 
> > The existing PCIe/PHY nodes are not strictly ordered by address. Current
> > order is:
> 
> Obviously we cannot even keep order of nodes when creating a new DTSI
> file from scratch.
> 
> But adding @f00000 after @1c10000 makes even less sense, regardless how
> bad existing code is. Don't make it worse!
> 
> This goes before phy@fa0000

Okay, will move phy@f00000 before phy@fa0000

- Qiang Yu

> 
> > 
> > - pcie4: pci@1bf0000
> > - pcie4_phy: phy@1bf6000
> > - pcie5: pci@1b40000
> > - pcie5_phy: phy@1b50000
> > - pcie6: pci@1c00000
> > - pcie6_phy: phy@1c06000
> > - pcie3b: pci@1b80000
> > - pcie3a: pci@1c10000 (added in this patch)
> > - pcie3a_phy: phy@f00000 (added in this patch)
> > - pcie3b_phy: phy@f10000
> > 
> > Do you want me to reorder these nodes to follow strict address order?
> 
> No, but don't add nodes randomly or following the previous broken order.
>
> Best regards,
> Krzysztof