Re: [PATCH v3 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC

[Nirmoy Das]

On Thu, 16 Apr 2026 01:45:04 +0000, Ankit Agrawal <ankita@xxxxxxxxxx> wrote:
> Add a CXL DVSEC-based readiness check for Blackwell-Next GPUs alongside
> the existing legacy BAR0 polling path. On probe and after reset, the
> driver reads the CXL Device DVSEC capability to determine whether the
> GPU memory is valid. This is checked by polling on the Memory_Active bit
> based on the Memory_Active_Timeout. Also check if MEM_INFO_VALID is set
> within 1 second per CXL spec 4.0 Tables 8-13. If not, return error.
>
> A static inline wrapper dispatches to the appropriate readiness check
> based on whether the CXL DVSEC capability is present.
>
> Add PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT to pci_regs.h for the timeout
> field encoding.
>
> Signed-off-by: Ankit Agrawal <ankita@xxxxxxxxxx>

Tested-and-Acked-by: Nirmoy Das <nirmoyd@xxxxxxxxxx>