Re: [PATCH] arm64: dts: qcom: glymur: Drop fake PCIe phy 3B

[Dmitry Baryshkov]

On Mon, Apr 20, 2026 at 03:36:17PM +0200, Krzysztof Kozlowski wrote:
> According to user manual / programming guide there is no separate PCIe
> phy 3A and 3B, but one 8-lane QMP PCIe Gen5 PHY which consists of two
> 4-lane blocks.  This is also visible in memory map, where the 0xf00000
> is marked as the main block with additional sub blocks for each 4-lane
> phys.
> 
> Describing the sub phys without the rest is not correct from hardware
> description, even if it works.

Is this the case for the other bifurcated PHYs?

> 
> Link: https://lore.kernel.org/r/20260420-optimistic-unnatural-stingray-80da35@quoll/
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/glymur-crd.dtsi |  5 ---
>  arch/arm64/boot/dts/qcom/glymur.dtsi     | 39 +-----------------------
>  2 files changed, 1 insertion(+), 43 deletions(-)
> 

-- 
With best wishes
Dmitry