Re: [PATCH] arm64: dts: renesas: rzt2h-n2h-evk: Configure eMMC/SDHI pins

[Geert Uytterhoeven]

Hi Fabrizio,

On Tue, 31 Mar 2026 at 16:52, Fabrizio Castro
<fabrizio.castro.jz@xxxxxxxxxxx> wrote:
> The HW user manual for the Renesas RZ/T2H and the RZ/N2H state
> that for SDR104, SDR50, and HS200 to work properly the eMMC/SDHI
> interface pins have to be configured as specified below:
> * SDn_CLK pin - drive strength: Ultra High, slew rate: fast
> * Other SDn_* pins: drive strength: High, slew rate: fast,
>   Schmitt trigger: disabled (not applicable to SDn_RST pins).
>
> Adjust the pin definitions accordingly.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>

According to Table 58.11 ("IO setting (DRCTLm register setting)
condition"), the recommended drive strength value for the SDn_CLK pins
depends on the transfer mode. So shouldn't this be changed at runtime,
depending on the type of SD card that is present, using different
pinctrl states?

Currently we have:

    &sdhi0 {
            pinctrl-0 = <&sdhi0_sd_pins>;
            pinctrl-1 = <&sdhi0_sd_pins>;
            pinctrl-names = "default", "state_uhs";
            ...
    };

I.e. it uses the same pinctrl state for all modes.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds