Re: [PATCH v2 1/4] perf/x86/intel: Don't write PEBS_ENABLED on host<=>guest xfers if CPU has isolation

[Peter Zijlstra]

On Thu, Apr 23, 2026 at 08:03:37AM -0700, Sean Christopherson wrote:
> When filling the list of MSRs to be loaded by KVM on VM-Enter and VM-Exit,
> *never* insert an entry for PEBS_ENABLED if the CPU properly isolates PEBS
> events, in which case disabling counters via PERF_GLOBAL_CTRL is sufficient
> to prevent unwanted PEBS events in the guest (or host).  Because perf loads
> PEBS_ENABLE with the unfiltered cpu_hw_events.pebs_enabled, i.e. with both
> host and guest masks, there is no need to load different values for the
> guest versus host, perf+KVM can and should simply control which counters
> are enabled/disabled via PERF_GLOBAL_CTRL.
> 
> Avoiding touching PEBS_ENABLED fixes a theorized bug where PEBS_ENABLED can
> end up with "stuck" bits if a PEBS event is throttled better generating the
> list and actually entering the guest (Intel CPUs can't arbtitrarily block
> NMIs). 

Supposedly writing 0 to GLOBAL_CTRL *should* serialize vs PMI on most
chips IIRC. That is something perf itself relies on. Once we've cleared
GLOBAL_CTRL we do not expect any PMIs.