Re: [PATCH RFC v4 6/7] drm/msm/adreno: add Adreno 810 GPU support
From: Alexander Koskovich
Date: Thu Apr 23 2026 - 16:27:48 EST
On Wednesday, April 22nd, 2026 at 9:04 AM, Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx> wrote:
>
>
> On 16-Apr-26 13:05, Alexander Koskovich wrote:
> > Add catalog entry and register configuration for the Adreno 810
> > found in Qualcomm SM7635 (Milos) based devices.
> >
> > Signed-off-by: Alexander Koskovich <akoskovich@xxxxx>
> > ---
> > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 296 ++++++++++++++++++++++++++++++
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +
> > 2 files changed, 301 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > index 550ff3a9b82e..1190804632d6 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > @@ -1799,6 +1799,259 @@ static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = {
> > };
> > DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist);
> >
> > +static const struct adreno_reglist_pipe a810_nonctxt_regs[] = {
>
> To align with the latest kgsl which includes all the latest
> recommendations, remove:
>
> { REG_A8XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
>
> { REG_A8XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
> { REG_A8XX_TPL1_DBG_ECO_CNTL1, 0x00000724, BIT(PIPE_NONE) },
>
> { REG_A8XX_UCHE_CACHE_WAYS, 0x00080000, BIT(PIPE_NONE) },
>
> { REG_A8XX_VSC_BIN_SIZE, 0x00010001, BIT(PIPE_NONE) },
>
> and add:
>
> (below RB_CCU_CNTL)
> { REG_A8XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
>
> (swap in place)
> { REG_A8XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) },
> { REG_A8XX_TPL1_DBG_ECO_CNTL1, 0x04000724, BIT(PIPE_NONE) },
>
> (below UCHE_CCHE_CACHE_WAYS)
> { REG_A8XX_UCHE_HW_DBG_CNTL, BIT(8), BIT(PIPE_NONE) },
>
> (below RB_GC_GMEM_PROTECT)
> { REG_A8XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
Just wanted to clarify if this was a typo, since you also asked for RB_CCU_DBG_ECO_CNTL below RB_CCU_CNTL as well.
>
> (The order doesn't actually matter but it'll be easier to diff)
>
> Konrad
>
Thanks,
Alex