Re: [PATCH v1 0/3] iommu/amd: Fix and improve SB IOAPIC IVRS validation

[Jörg Rödel]

Suravee, Vasant, could you please have a look at this series?

Thanks,

	Joerg

On Mon, Apr 06, 2026 at 11:40:06PM +0800, Wei Wang wrote:
> The check_ioapic_information() function validates that the Southbridge
> (SB) IOAPIC is correctly listed in the IVRS table before enabling
> Interrupt Remapping (IR). If validation fails, IR is disabled to avoid
> IOMMU dropping interrupts from unmapped devices.
> 
> This series fixes three independent bugs in that function:
> 
> Patch 1 fixes a logic error where successfully detecting the SB IOAPIC
> resets a 'ret' flag that was previously cleared by an unmapped secondary
> (i.e., non-SB) IOAPIC. This causes IR to stay enabled when it should have
> been disabled, leading to localized device hangs.
> 
> Patch 2 fixes a false positive: the SB IOAPIC was identified solely by
> its devid matching the hardcoded value (00:14.0). If a buggy BIOS assigns
> that devid to a secondary IOAPIC in the IVRS while the real SB IOAPIC gets
> a different mapping, the check passes anyway and IR is left enabled. The
> system timer's interrupts then get dropped by the IOMMU, causing a silent
> boot hang. The fix identifies the SB IOAPIC by its APIC ID (the IOAPIC
> that owns GSI 0) before matching its devid.
> 
> Patch 3 removes the hardcoded SB IOAPIC devid entirely and replaces it
> with a dynamic PCI config‑space check. The SB IOAPIC resides in the FCH
> (Fusion Controller Hub / Southbridge), which typically exposes itself as
> an SMBus controller function. For example:
> 
> AMD Genoa:
> 00:14.0 SMBus: Advanced Micro Devices, Inc. FCH SMBus Controller
> 
> Hygon Gen4:
> 00:0b.0 SMBus: Chengdu Haiguang IC Design Co., Ltd. FCH SMBus Controller
> 
> The PCI class code at a given BDF is a stable, specification-defined
> property. Using it to identify an FCH function avoids maintaining
> per-vendor/per-generation hardcoded device IDs that must be updated for
> new platforms, while producing the same safe fallback (IR disabled) if
> the check ever fails.
> 
> Wei Wang (3):
>   iommu/amd: Prevent SB IOAPIC from overriding IVRS validation errors
>   iommu/amd: Fix false positive in SB IOAPIC IVRS validation
>   iommu/amd: Dynamically verify Southbridge IOAPIC via PCI config space
> 
>  drivers/iommu/amd/init.c | 51 ++++++++++++++++++++++++++++++++++------
>  1 file changed, 44 insertions(+), 7 deletions(-)
> 
> 
> base-commit: 2febe6e6ee6e34c7754eff3c4d81aa7b0dcb7979
> -- 
> 2.51.0
>