Re: [PATCH v2 2/3] x86/apic: Introduce a variable to track the number of EILVT registers

[Christian Ludloff]

> + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC))
> + apic_eilvt_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT));

BKDG #21656, #21922, and #24141 for K7 were not published.
If you find them internally at AMD, consider publishing them.  :)
That way they could be archived, and referenced from then on.

BKDG #26094 for K8 Fam Fh DDR1 documents 4 extended LVTs.
BKDG #32559 for K8 Fam Fh DDR2 documents 1 extended LVT.
BKDG #41256 for K8 Fam 11h (LG) documents 4 extended LVTs.

Fam 10h/12h, 14h and 16h, and 15h all have 4 – no surprises.

The Fam 10h BKDG (#31116) has an explicit entry in its "Major
Changes Relative to Family 0Fh Processors" section: "Number
of extended LVT interrupts in APIC increased to 4." – AMD may
want to clarify what was correct vs not for those old K8 models.

> + if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> + apic_eilvt_count = APIC_EILVT_NR_AMD_10H;

This seems... unsafe?

--
C.