[PATCH v2 37/37] arm64: dts: qcom: msm8996: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru
Date: Thu Jun 11 2026 - 01:12:18 EST
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0, pcie1_port0, and pcie2_port0, adding labels to these
nodes to allow board-level overrides. Move perst-gpios/wake-gpios
from the controller overrides to the respective port nodes in the
board files, renaming perst-gpios to reset-gpios to match the binding
used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 15 ++++++++++++---
.../arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi | 5 ++++-
.../boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 7 +++++--
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 4 +++-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 21 +++++++++------------
5 files changed, 33 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 0c076852b494..ad435a13ba24 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -458,23 +458,32 @@ hdmi_ddc_suspend: hdmi-ddc-suspend-state {
&pcie0 {
status = "okay";
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+};
+
&pcie1 {
status = "okay";
- perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
+};
+
&pcie2 {
status = "okay";
- perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
+&pcie2_port0 {
+ reset-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
index a4dcc88bb01f..7a3f8afae22d 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
@@ -210,12 +210,15 @@ &mss_pil {
};
&pcie0 {
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
status = "okay";
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
index 5b42c266557a..20b5eeef46e4 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
@@ -191,13 +191,16 @@ &mmcc {
};
&pcie0 {
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&pm8994_l28>;
status = "okay";
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
vdda-phy-supply = <&pm8994_l28>;
vdda-pll-supply = <&pm8994_l12>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
index 2abcc733dad8..3c70a9be45d2 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
@@ -278,8 +278,10 @@ &pcie0 {
/* Supplied by vdd_3v3, but choose wlan_en to drive enable pin high */
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
+};
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 2f67e665996f..8db1448e5e61 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1900,9 +1900,6 @@ pcie0: pcie@600000 {
<0x0c100000 0x100000>;
reg-names = "parf", "dbi", "elbi","config";
- phys = <&pciephy_0>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
@@ -1951,7 +1948,7 @@ pcie0: pcie@600000 {
"bus_master",
"bus_slave";
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -1959,6 +1956,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pciephy_0>;
};
};
@@ -1977,9 +1976,6 @@ pcie1: pcie@608000 {
reg-names = "parf", "dbi", "elbi","config";
- phys = <&pciephy_1>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
@@ -2028,7 +2024,7 @@ pcie1: pcie@608000 {
"bus_master",
"bus_slave";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2036,6 +2032,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pciephy_1>;
};
};
@@ -2052,9 +2050,6 @@ pcie2: pcie@610000 {
reg-names = "parf", "dbi", "elbi","config";
- phys = <&pciephy_2>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
@@ -2102,7 +2097,7 @@ pcie2: pcie@610000 {
"bus_master",
"bus_slave";
- pcie@0 {
+ pcie2_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2110,6 +2105,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pciephy_2>;
};
};
};
--
2.34.1