[PATCH v2 27/37] arm64: dts: qcom: sc8280xp: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru
Date: Thu Jun 11 2026 - 01:12:28 EST
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcie2a_port0, pcie2b_port0, pcie3a_port0, pcie3b_port0,
and pcie4_port0 nodes. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board files,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 24 +++++++++++++--------
.../boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 14 ++++++------
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 22 +++++++++++--------
.../boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 22 +++++++++++--------
.../boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 14 ++++++------
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++++++++-------------
6 files changed, 67 insertions(+), 54 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index c53e00cae465..4c2700e9b00d 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -628,9 +628,6 @@ keyboard@68 {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
@@ -639,6 +636,11 @@ &pcie2a {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -647,9 +649,6 @@ &pcie2a_phy {
};
&pcie3a {
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-names = "default";
@@ -658,6 +657,11 @@ &pcie3a {
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
&pcie3a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -668,9 +672,6 @@ &pcie3a_phy {
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-names = "default";
@@ -679,6 +680,11 @@ &pcie4 {
status = "okay";
};
+&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+};
+
&pcie4_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts
index 9819454abe13..1aba18ae301d 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts
@@ -739,9 +739,6 @@ &mdss0_dp1_out {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@@ -750,6 +747,11 @@ &pcie2a {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -760,9 +762,6 @@ &pcie2a_phy {
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@@ -772,6 +771,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index d84ca010ab9d..603184a7c06c 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -933,9 +933,6 @@ keyboard@68 {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
@@ -944,6 +941,11 @@ &pcie2a {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -952,9 +954,6 @@ &pcie2a_phy {
};
&pcie3a {
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-names = "default";
@@ -963,6 +962,11 @@ &pcie3a {
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
&pcie3a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -973,9 +977,6 @@ &pcie3a_phy {
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-names = "default";
@@ -985,6 +986,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
index f2b4470d4407..4dd287e6fb95 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
@@ -486,9 +486,6 @@ &mdss0_dp1_out {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@@ -497,6 +494,11 @@ &pcie2a {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -505,9 +507,6 @@ &pcie2a_phy {
};
&pcie3a {
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-0 = <&pcie3a_default>;
@@ -516,6 +515,11 @@ &pcie3a {
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
&pcie3a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -526,9 +530,6 @@ &pcie3a_phy {
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@@ -538,6 +539,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
index 00bbeeef6f14..21438e638da6 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
@@ -624,9 +624,6 @@ &mdss0_dp2_phy {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@@ -635,6 +632,11 @@ &pcie2a {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l4d>;
vdda-pll-supply = <&vreg_l6d>;
@@ -645,9 +647,6 @@ &pcie2a_phy {
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@@ -657,6 +656,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 761f229e8f47..c59d7b499008 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -2220,9 +2220,6 @@ pcie4: pcie@1c00000 {
power-domains = <&gcc PCIE_4_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie4_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie4_port0: pcie@0 {
@@ -2233,6 +2230,8 @@ pcie4_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie4_phy>;
};
};
@@ -2331,9 +2330,6 @@ pcie3b: pcie@1c08000 {
power-domains = <&gcc PCIE_3B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie3b_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie3b_port0: pcie@0 {
@@ -2344,6 +2340,8 @@ pcie3b_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie3b_phy>;
};
};
@@ -2442,9 +2440,6 @@ pcie3a: pcie@1c10000 {
power-domains = <&gcc PCIE_3A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie3a_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie3a_port0: pcie@0 {
@@ -2455,6 +2450,8 @@ pcie3a_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie3a_phy>;
};
};
@@ -2556,9 +2553,6 @@ pcie2b: pcie@1c18000 {
power-domains = <&gcc PCIE_2B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie2b_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie2b_port0: pcie@0 {
@@ -2569,6 +2563,8 @@ pcie2b_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie2b_phy>;
};
};
@@ -2667,9 +2663,6 @@ pcie2a: pcie@1c20000 {
power-domains = <&gcc PCIE_2A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie2a_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie2a_port0: pcie@0 {
@@ -2680,6 +2673,8 @@ pcie2a_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie2a_phy>;
};
};
--
2.34.1