Re: [PATCH v2 1/3] x86/CPU/AMD: Avoid racy updates to MSR_K7_HWCR in set_cpuid_faulting()

[Jim Mattson]

On Fri, Jun 12, 2026 at 3:30 PM Yosry Ahmed <yosry@xxxxxxxxxx> wrote:
>
> On Fri, Jun 12, 2026 at 2:57 PM Jim Mattson <jmattson@xxxxxxxxxx> wrote:
...
> > + * Context: Any context except NMI. Disabling interrupts does not
> > + *          serialize against an NMI, so NMI handlers must not write
> > + *          MSR_K7_HWCR.
>
> Might be more useful to WARN if in_nmi()?

I concur.

> > + *
> > + * Return: 0 on success, negative error code if an MSR access faults.
> > + */
> > +int amd_update_hwcr(u64 clear, u64 set)
> > +{
> > +       unsigned long flags;
> > +       u64 oldval, newval;
> > +       int ret;
> > +
> > +       local_irq_save(flags);
> > +       ret = rdmsrq_safe(MSR_K7_HWCR, &oldval);
> > +       if (ret)
> > +               goto out;
> > +
> > +       newval = (oldval & ~clear) | set;
> > +
> > +       if (newval != oldval)
> > +               ret = wrmsrq_safe(MSR_K7_HWCR, newval);
>
> Can we reuse msr_set_bit() and msr_clear_bit() here?

Yes. I tried to make it more general, but none of the current users
want to modify more than one bit.

I'll try to get v3 out this week.