Re: [PATCH] cpufreq: tegra124: Disable DFLL clock on removal

[Myeonghun Pak]

Thanks for reviewing.

Yes, after tegra124_cpu_switch_to_dfll() succeeds, the CPU clock is
parented to DFLL. The intended cleanup path is not to disable DFLL while
the CPU is still using it, but to first reparent the CPU clock back to
PLLP and only then disable DFLL.

That is why the helper does:

    clk_set_parent(priv->cpu_clk, priv->pllp_clk);
    clk_disable_unprepare(priv->dfll_clk);

This follows the same ordering as the suspend path, where the driver also
switches the CPU clock source to PLLP before disabling DFLL.

2026년 6월 27일 (토) 오전 2:18, Jon Hunter <jonathanh@xxxxxxxxxx>님이 작성:
>
>
>
> On 26/06/2026 10:30, Myeonghun Pak wrote:
> > tegra124_cpu_switch_to_dfll() enables the DFLL clock before switching
> > the CPU clock parent to it. If cpufreq_dt_pdev_register() fails after
> > that point, or when the driver is removed, the driver only drops clock
> > references and never disables the enabled DFLL clock.
>
> So after this change, if we successful switch to the DFLL, but we fail
> to register the device, we disable the DFLL. That does not sound good
> because the CPU will be using that clock at the time. I am not sure what
> the value in this change really is.
>
> Jon
>
> --
> nvpublic
>