Re: [PATCH v4 0/2] RISC-V IOMMU HPM support

[fangyu . yu]

>This series implements support for the RISC-V IOMMU hardware performance
>monitor.
>
>The RISC-V IOMMU PMU driver is implemented as an auxiliary device driver
>created by the parent RISC-V IOMMU driver. Therefore, the child driver
>can obtain resources and information from the parent device, such as
>the MMIO base address and IRQ number.
>

Hi Zong,

I tested this series on a riscv64 QEMU with a QEMU NVMe device.
The NVMe device was enumerated correctly, and the RISC-V IOMMU PMU
events could be counted successfully while running I/O to the NVMe disk.

The following command completed successfully:

  perf stat -a \
    -e riscv_iommu_pmu_3010000.iommu/tlb_miss/ \
    -e riscv_iommu_pmu_3010000.iommu/cycle/ \
    -e riscv_iommu_pmu_3010000.iommu/untranslated_req/ \
    -e riscv_iommu_pmu_3010000.iommu/s_vs_pt_walks/ \
    dd if=/dev/nvme0n1 of=/dev/null bs=1M count=100

100+0 records in
100+0 records out
104857600 bytes (105 MB, 100 MiB) copied, 1.43612 s, 73.0 MB/s

 Performance counter stats for 'system wide':

             26449      riscv_iommu_pmu_3010000.iommu/tlb_miss/                                      
            256659      riscv_iommu_pmu_3010000.iommu/cycle/                                      
             32063      riscv_iommu_pmu_3010000.iommu/untranslated_req/                                      
            132245      riscv_iommu_pmu_3010000.iommu/s_vs_pt_walks/                                      

       1.464510700 seconds time elapsed

Tested-by: Fangyu Yu <fangyu.yu@xxxxxxxxxxxxxxxxx>