Re: [PATCH v5 3/6] arm64: dts: qcom: shikra: Add CCI definitions

[Loic Poulain]

On Mon, Jul 13, 2026 at 11:29 AM Nihal Kumar Gupta
<nihal.gupta@xxxxxxxxxxxxxxxx> wrote:
>
> Qualcomm Shikra SoC has one Camera Control Interface (CCI)
> containing two I2C hosts.
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@xxxxxxxxxx>
> Signed-off-by: Nihal Kumar Gupta <nihal.gupta@xxxxxxxxxxxxxxxx>

Reviewed-by: Loic Poulain <loic.poulain@xxxxxxxxxxxxxxxx>

> ---
>  arch/arm64/boot/dts/qcom/shikra.dtsi | 70 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index 6335caca329808ee04d9067f1f95e8075e2fc3ed..18da1380e52acdd8813625eaceac796e342efd16 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
> @@ -355,6 +355,38 @@ qup_uart0_default: qup-uart0-default-state {
>                                 bias-disable;
>                         };
>
> +                       cci_i2c0_default: cci-i2c0-default-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio36", "gpio37";
> +                               function = "cci_i2c0";
> +                               drive-strength = <2>;
> +                               bias-pull-up;
> +                       };
> +
> +                       cci_i2c0_sleep: cci-i2c0-sleep-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio36", "gpio37";
> +                               function = "cci_i2c0";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
> +                       cci_i2c1_default: cci-i2c1-default-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio41", "gpio42";
> +                               function = "cci_i2c1";
> +                               drive-strength = <2>;
> +                               bias-pull-up;
> +                       };
> +
> +                       cci_i2c1_sleep: cci-i2c1-sleep-state {
> +                               /* SDA, SCL */
> +                               pins = "gpio41", "gpio42";
> +                               function = "cci_i2c1";
> +                               drive-strength = <2>;
> +                               bias-pull-down;
> +                       };
> +
>                         sdc1_state_on: sdc1-on-state {
>                                 clk-pins {
>                                         pins = "sdc1_clk";
> @@ -702,6 +734,44 @@ port@1 {
>                                         reg = <1>;
>                                 };
>                         };
> +
> +               };
> +
> +               cci: cci@5c1b000 {
> +                       compatible = "qcom,shikra-cci", "qcom,msm8996-cci";
> +                       reg = <0x0 0x05c1b000 0x0 0x1000>;
> +
> +                       interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING 0>;
> +
> +                       clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
> +                                <&gcc GCC_CAMSS_CCI_0_CLK>;
> +                       clock-names = "ahb",
> +                                     "cci";
> +
> +                       power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
> +
> +                       pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>;
> +                       pinctrl-1 = <&cci_i2c0_sleep &cci_i2c1_sleep>;
> +                       pinctrl-names = "default", "sleep";
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       status = "disabled";
> +
> +                       cci_i2c0: i2c-bus@0 {
> +                               reg = <0>;
> +                               clock-frequency = <400000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
> +
> +                       cci_i2c1: i2c-bus@1 {
> +                               reg = <1>;
> +                               clock-frequency = <400000>;
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                       };
>                 };
>
>                 qupv3_0: geniqup@4ac0000 {
>
> --
> 2.34.1
>