Re: [PATCH 3/7] irqchip/irq-qcom-mpm: Prepare common access path for timer and pin regs

[Konrad Dybcio]

On 7/13/26 12:25 PM, Sneh Mankad wrote:
> The vMPM layout starts with two timer registers followed by pin register
> banks (ENABLE/FALLING/RISING/POLARITY/STATUS), each with reg_stride
> number of entries.
> 
> Use qcom_mpm_offset() as the common addressing helper for both timer and
> pin register accesses based on that layout.
> 
> vMPM has MPM_REG_* values represented as contiguous register IDs,
> hence replace the macros with enum qcom_mpm_reg and modify the accessor
> helpers accordingly.
> 
> Signed-off-by: Sneh Mankad <sneh.mankad@xxxxxxxxxxxxxxxx>
> ---

[...]

> +static unsigned int qcom_mpm_offset(struct qcom_mpm_priv *priv, enum qcom_mpm_reg reg,
> +				    unsigned int index)
> +{
> +	unsigned int reg_offset;
> +
> +	/*
> +	 * Per the vMPM register map, TIMER[0..1] starts at register index 0 and all pin-specific
> +	 * registers start after the two TIMER regs. Pin-specific register IDs start at
> +	 * MPM_REG_ENABLE, so subtract it to convert to a zero-based pin-register group index.
> +	 */
> +	if (reg == MPM_REG_TIMER)
> +		reg_offset = index;
> +	else
> +		reg_offset = MPM_TIMER_REGS +
> +			 (reg - MPM_REG_ENABLE) * priv->reg_stride + index;
> +
> +	return reg_offset * sizeof(u32);

I think this comment is superfluous given the visual representation of
the register space just a couple dozen lines above

Maybe this could be a little easier to follow written this way:

s/MPM_TIMER_REGS/MPM_NUM_TIMER_REGS

reg_offset = 0;

if (reg != MPM_REG_TIMER) {
	reg_offset += MPM_NUM_TIMER_REGS;
	reg_offset += (reg - MPM_REG_ENABLE) * priv->reg_stride;
}

reg_offset += index;

Konrad