Re: [PATCH 1/1] iommu/vt-d: Disallow SVA if page walk is not coherent

[Samiullah Khawaja]

On Thu, Jul 16, 2026 at 01:35:53PM +0800, Lu Baolu wrote:
> Hardware implementations report Scalable-Mode Page-walk Coherency Support
> via the SMPWCS field in the extended capability register. If the hardware
> does not support page-walk coherency, a clflush is required every time
> the page table entries (which are walked by the IOMMU hardware) are
> updated.
>
> In the SVA case, page tables are managed by the CPU mm core, not by the
> IOMMU driver. Because the IOMMU driver has no way of knowing whether the
> CPU page table management code has ensured coherency via clflush, the
> driver must deny SVA if the hardware does not support coherent paging.
>
> Fixes: ff3dc6521f78 ("iommu/vt-d: Fix CPU and IOMMU SVM feature matching checks")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>
> ---
> drivers/iommu/intel/svm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c
> index 0636987f03c8..432e35723ce9 100644
> --- a/drivers/iommu/intel/svm.c
> +++ b/drivers/iommu/intel/svm.c
> @@ -27,7 +27,7 @@
>
> void intel_svm_check(struct intel_iommu *iommu)
> {
> -	if (!pasid_supported(iommu))
> +	if (!pasid_supported(iommu) || !ecap_smpwc(iommu->ecap))
> 		return;
>
> 	if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
> --
> 2.43.0

Reviewed-by: Samiullah Khawaja <skhawaja@xxxxxxxxxx>

Thanks,
Sami