RE: [PATCH 1/1] iommu/vt-d: Disallow SVA if page walk is not coherent

[Tian, Kevin]

> From: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>
> Sent: Thursday, July 16, 2026 1:36 PM
> 
> Hardware implementations report Scalable-Mode Page-walk Coherency
> Support
> via the SMPWCS field in the extended capability register. If the hardware
> does not support page-walk coherency, a clflush is required every time
> the page table entries (which are walked by the IOMMU hardware) are
> updated.
> 
> In the SVA case, page tables are managed by the CPU mm core, not by the
> IOMMU driver. Because the IOMMU driver has no way of knowing whether
> the
> CPU page table management code has ensured coherency via clflush, the
> driver must deny SVA if the hardware does not support coherent paging.
> 
> Fixes: ff3dc6521f78 ("iommu/vt-d: Fix CPU and IOMMU SVM feature
> matching checks")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>

Reviewed-by: Kevin Tian <kevin.tian@xxxxxxxxx>