Re: [RFC PATCH] clk: qcom: hfpll: return lock timeout from enable paths

[Konrad Dybcio]

On 7/8/26 6:04 PM, Antony Kurniawan Soemardi wrote:
> On 7/6/2026 5:58 PM, Konrad Dybcio wrote:
>> On 7/4/26 11:02 AM, Antony Kurniawan Soemardi wrote:

[...]

>> Can you check the state of the gcc_base+0x3420 register before and after
>> the /* De-assert active-low PLL reset. */ line?
> 
> I assume gcc_base is regmap on clk-hfpll.c, I dumped 0x3400 to 0x3420:
> 
> [   21.089748] HFPLL hfpll_l2 mode_reg=0x3400 (before reset) regs:
> [   21.089775]  3400:00000002
> [   21.090300]  3404:7845c665
> [   21.095944]  3408:00000000
> [   21.098714]  340c:00000000
> [   21.101404]  3410:00000001
> [   21.104098]  3414:0108c000
> [   21.106787]  3418:00000000
> [   21.109478]  341c:00000000
> [   21.112169]  3420:00000703
> [   21.114858]
> [   21.120243] HFPLL hfpll_l2 mode_reg=0x3400 (after reset) regs:
> [   21.120262]  3400:00000006
> [   21.121903]  3404:7845c665
> [   21.127540]  3408:00000000
> [   21.130228]  340c:00000000
> [   21.132916]  3410:00000001
> [   21.135605]  3414:0108c000
> [   21.138299]  3418:00000000
> [   21.140993]  341c:00000006
> [   21.143681]  3420:00000703

Okay, can you try dumping the same register from a running device on
downstream? The only change in values that we're seeing is BIT(2)
being set in 0x3400 (which means "set the RESET_N bit", a.k.a.
"request un-stopping the PLL")

Konrad