Re: [PATCH v5 0/3] Add QMP PCIe multiple link-mode PHY support

[Krzysztof Kozlowski]

On Fri, Jul 17, 2026 at 02:58:32AM -0700, Qiang Yu wrote:
> Hi all,
> 
> Some QMP PCIe PHY hardware blocks can be configured through a link-mode
> register into different link topologies, such as a single wide link, or
> multiple independent narrower links (e.g. x8 or x4+x4 mode on the Glymur
> PCIe3 PHY).
> 
> Earlier revisions tried to extend the existing single-instance
> phy-qcom-qmp-pcie.c driver to cover this hardware. That added a large
> amount of conditional, multi-PHY logic to a driver whose data model
> assumes one PHY per node.
> 
> This series adds a dedicated PHY provider driver,
> phy-qcom-qmp-pcie-multiphy.c:
> 
> A single PHY provider node describes the shared hardware block. A new
> "qcom,link-mode" property points at the TCSR syscon register that reports
> the active topology; the driver reads it once at probe. #phy-cells = <1>
> lets consumers pass a logical PHY index to obtain their sub-PHY. Match
> data is indexed by link mode, and each link mode has its own array of
> per-PHY config tables, so one shared provider exposes a different set of
> logical PHYs depending on the active mode. The driver inherits the PHY
> settings and link mode already programmed by UEFI, so only the no-CSR
> reset is used, and no PHY setting tables or related structures are
> defined. Each sub-PHY owns its register regions and power domain, so in a
> bifurcated mode the links are brought up, and powered independently.
> 
> The driver is implemented and validated on Glymur, and is intended to
> be extensible to other multi-mode QMP PCIe PHYs.
> 
> This series depends on a prerequisite patch by Krzysztof Kozlowski:
> https://lore.kernel.org/r/20260420133616.88740-2-krzysztof.kozlowski@xxxxxxxxxxxxxxxx

There was a v2, still not applied I think:
https://lore.kernel.org/all/20260609141608.354186-2-krzysztof.kozlowski@xxxxxxxxxxxxxxxx/

Best regards,
Krzysztof