Re: [PATCH v5 1/3] dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY

[Qiang Yu]

On Sun, Jul 19, 2026 at 08:50:00AM +0200, Krzysztof Kozlowski wrote:
> On Fri, Jul 17, 2026 at 02:58:33AM -0700, Qiang Yu wrote:
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-pcie-multiphy.yaml b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-pcie-multiphy.yaml
> > new file mode 100644
> > index 000000000000..73550f77e9b6
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-pcie-multiphy.yaml
> 
> Filename: qcom,glymur-qmp-gen5x8-pcie-phy.yaml
> 
Okay, will rename the file to qcom,glymur-qmp-gen5x8-pcie-phy.yaml.

> > @@ -0,0 +1,176 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/qcom,glymur-qmp-pcie-multiphy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm QMP PCIe multiple link-mode PHY controller (PCIe, Glymur)
> > +
> > +maintainers:
> > +  - Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> > +  - Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxxxxxxxx>
> > +
> > +description: |
> > +  The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the
> > +  PCIe3a/PCIe3b controllers. This block supports two link modes, selected
> > +  at runtime via a TCSR syscon register:
> > +
> > +  1. x8 - a single 8-lane PHY instance is exposed (PCIe3a only)
> > +  2. x4+x4 - two independent 4-lane PHY instances are exposed (PCIe3a and
> > +     PCIe3b)
> > +
> > +  The node always describes both PHY instances ("port a" and "port b"),
> > +  regardless of which link mode is active on the board.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - qcom,glymur-qmp-gen5x8-pcie-phy
> > +
> > +  reg:
> > +    minItems: 2
> 
> Dop

Will drop minItems: 2

> 
> > +    maxItems: 2
> > +
> > +  reg-names:
> > +    items:
> > +      - const: port_a
> > +      - const: port_b
> > +
> > +  clocks:
> > +    minItems: 10
> 
> Drop
>

Will drop minItems: 10

> > +    maxItems: 10
> > +
> > +  clock-names:
> > +    items:
> > +      - const: aux
> > +      - const: cfg_ahb
> > +      - const: ref
> > +      - const: rchng
> > +      - const: pipe
> > +      - const: phy_b_aux
> > +      - const: cfg_ahb_b
> > +      - const: rchng_b
> > +      - const: pipe_b
> > +      - const: pipediv2_b
> > +
> > +  power-domains:
> > +    minItems: 2
> 
> Drop

Will drop minItems: 2

> 
> > +    maxItems: 2
> > +
> > +  power-domain-names:
> > +    items:
> > +      - const: phy_a_gdsc
> 
> port_a

Will rename it to port_a.

> 
> > +      - const: phy_b_gdsc
> 
> port_b

Will rename it to port_b.

> 
> > +
> > +  resets:
> > +    minItems: 4
> 
> Drop

Will drop minItems: 4

> 
> > +    maxItems: 4
> > +
> > +  reset-names:
> > +    items:
> > +      - const: phy_a
> 
> port_a

Will rename it to port_a.

> 
> > +      - const: phy_a_nocsr
> 
> port_a_nocsr
> 
> etc.

Will rename them to port_a_nocsr, port_b and port_b_nocsr.

> 
> > +      - const: phy_b
> > +      - const: phy_b_nocsr
> > +
> > +  vdda-phy-supply: true
> > +
> > +  vdda-pll-supply: true
> > +
> > +  vdda-refgen0p9-supply: true
> > +
> > +  vdda-refgen1p2-supply: true
> > +
> > +  qcom,link-mode:
> > +    description:
> > +      Reference to a register in the TCSR syscon that reports the link
> > +      mode the PCIe PHY is currently configured for, either a single x8
> > +      link or two independent x4 links. The link mode is programmed by
> > +      firmware before Linux boots; this property is only used to read
> > +      the active link mode, specified as a phandle to the syscon and
> > +      the register offset.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    items:
> > +      - items:
> > +          - description: phandle of TCSR syscon
> > +          - description: offset of link mode register
> > +
> > +  "#clock-cells":
> > +    const: 1
> > +
> > +  clock-output-names:
> > +    items:
> > +      - description: Name of the PHY A pipe clock output.
> > +      - description: Name of the PHY B pipe clock output.
> > +
> > +  "#phy-cells":
> > +    const: 1
> 
> You should explain in description the meaning of cell value. Or provide
> filename of header with constants.
>
Okay, will add a description explaining the cell value in the next
version:

"#phy-cells":
  const: 1
  description:
    The cell is the index of the sub-PHY within the active link
    mode, e.g. on Glymur, 0 for "port a" and 1 for "port b" in
    x4x4 mode, and only index 0 (the single wide PHY) is valid in
    x8 mode.

> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +  - clocks
> > +  - clock-names
> > +  - power-domains
> > +  - power-domain-names
> > +  - resets
> > +  - reset-names
> > +  - vdda-phy-supply
> > +  - vdda-pll-supply
> > +  - vdda-refgen0p9-supply
> > +  - vdda-refgen1p2-supply
> > +  - qcom,link-mode
> > +  - "#clock-cells"
> > +  - clock-output-names
> > +  - "#phy-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/qcom,glymur-gcc.h>
> > +    #include <dt-bindings/clock/qcom,glymur-tcsr.h>
> > +
> > +    pcie3_phy: phy@f00000 {
> 
> Drop unused label.
>

Will drop the unused "pcie3_phy:" label from the example.

> The old 5x4 glymur compatible could be deprecated as well, but fine for
> me without doing so.
>

The old 5x4 glymur compatible is also required by PCIe5 PHY, so I'll leave
it as-is.

- Qiang Yu