[PATCH v2 2/9] arm64: dts: imx8ulp: Add I3C2 controller node
From: Peng Fan (OSS)
Date: Mon Jul 20 2026 - 10:14:58 EST
From: Peng Fan <peng.fan@xxxxxxx>
Add the I3C2 (i3c-master@29360000) node to the imx8ulp device tree using
the Silvaco I3C master IP. Configure PCC3-gated clock with SOSC DIV2 as
parent at 24 MHz for pclk and fast_clk. slow_clk uses a dummy clock.
Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 1ab4ab270dc2d..cb0d73327d86c 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -361,6 +361,22 @@ tpm5: tpm@29340000 {
status = "disabled";
};
+ i3c2: i3c@29360000 {
+ compatible = "silvaco,i3c-master-v1";
+ reg = <0x29360000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ clocks = <&pcc3 IMX8ULP_CLK_I3C2>,
+ <&pcc3 IMX8ULP_CLK_I3C2>,
+ <&cgc1 IMX8ULP_CLK_DUMMY>;
+ clock-names = "pclk", "fast_clk", "slow_clk";
+ assigned-clocks = <&pcc3 IMX8ULP_CLK_I3C2>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
+ assigned-clock-rates = <24000000>;
+ status = "disabled";
+ };
+
lpi2c4: i2c@29370000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29370000 0x10000>;
--
2.34.1