Re: [PATCH 1/1] iommu/vt-d: Disallow SVA if page walk is not coherent

[Will Deacon]

On Thu, 16 Jul 2026 13:35:53 +0800, Lu Baolu wrote:
> Hardware implementations report Scalable-Mode Page-walk Coherency Support
> via the SMPWCS field in the extended capability register. If the hardware
> does not support page-walk coherency, a clflush is required every time
> the page table entries (which are walked by the IOMMU hardware) are
> updated.
> 
> In the SVA case, page tables are managed by the CPU mm core, not by the
> IOMMU driver. Because the IOMMU driver has no way of knowing whether the
> CPU page table management code has ensured coherency via clflush, the
> driver must deny SVA if the hardware does not support coherent paging.
> 
> [...]

Applied to iommu (fixes), thanks!

[1/1] iommu/vt-d: Disallow SVA if page walk is not coherent
      https://git.kernel.org/iommu/c/780dfed68862

Cheers,
-- 
Will

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