Re: [PATCH v6 1/6] dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY

[Manivannan Sadhasivam]

On Wed, Jul 22, 2026 at 07:30:18PM -0700, Qiang Yu wrote:
> Add qcom,glymur-qmp-pcie-multiphy.yaml as a standalone binding
> for the Glymur Gen5 PCIe PHY hardware block. This block supports two
> link modes, selected at runtime via a TCSR syscon register:
> 
> 1. x8 - a single 8-lane PHY instance is exposed
> 2. x4+x4 - two independent 4-lane PHY instances are exposed
> 
> Keep this as a separate schema from qcom,sc8280xp-qmp-pcie-phy.yaml
> rather than folding it into the shared compatible list there, since the
> two PHY instances active in x8 mode require twice as many clocks,
> resets, and power-domains as any other entry in that file, and adding
> Glymur-specific properties like qcom,link-mode and reg-names there
> would only apply to this one compatible.
> 
> Document the required clocks, resets, and power-domains for both PHY
> instances, and use #phy-cells = <1>, where the cell value is the PHY
> index within the active link mode.
> 
> Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>

Acked-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>

- Mani

> ---
>  .../phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml       | 177 +++++++++++++++++++++
>  1 file changed, 177 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml
> new file mode 100644
> index 000000000000..759f7f979dc6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml
> @@ -0,0 +1,177 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QMP PCIe multiple link-mode PHY controller (PCIe, Glymur)
> +
> +maintainers:
> +  - Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> +  - Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxxxxxxxx>
> +
> +description: |
> +  The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the
> +  PCIe3a/PCIe3b controllers. This block supports two link modes, selected
> +  at runtime via a TCSR syscon register:
> +
> +  1. x8 - a single 8-lane PHY instance is exposed (PCIe3a only)
> +  2. x4+x4 - two independent 4-lane PHY instances are exposed (PCIe3a and
> +     PCIe3b)
> +
> +  The node always describes both PHY instances ("port a" and "port b"),
> +  regardless of which link mode is active on the board.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,glymur-qmp-gen5x8-pcie-phy
> +
> +  reg:
> +    maxItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: port_a
> +      - const: port_b
> +
> +  clocks:
> +    maxItems: 10
> +
> +  clock-names:
> +    items:
> +      - const: aux
> +      - const: cfg_ahb
> +      - const: ref
> +      - const: rchng
> +      - const: pipe
> +      - const: phy_b_aux
> +      - const: cfg_ahb_b
> +      - const: rchng_b
> +      - const: pipe_b
> +      - const: pipediv2_b
> +
> +  power-domains:
> +    maxItems: 2
> +
> +  power-domain-names:
> +    items:
> +      - const: port_a
> +      - const: port_b
> +
> +  resets:
> +    maxItems: 4
> +
> +  reset-names:
> +    items:
> +      - const: port_a
> +      - const: port_a_nocsr
> +      - const: port_b
> +      - const: port_b_nocsr
> +
> +  vdda-phy-supply: true
> +
> +  vdda-pll-supply: true
> +
> +  vdda-refgen0p9-supply: true
> +
> +  vdda-refgen1p2-supply: true
> +
> +  qcom,link-mode:
> +    description:
> +      Reference to a register in the TCSR syscon that reports the link
> +      mode the PCIe PHY is currently configured for, either a single x8
> +      link or two independent x4 links. The link mode is programmed by
> +      firmware before Linux boots; this property is only used to read
> +      the active link mode, specified as a phandle to the syscon and
> +      the register offset.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle of TCSR syscon
> +          - description: offset of link mode register
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  clock-output-names:
> +    items:
> +      - description: Name of the PHY A pipe clock output.
> +      - description: Name of the PHY B pipe clock output.
> +
> +  "#phy-cells":
> +    const: 1
> +    description:
> +      The cell is the index of the sub-PHY within the active link
> +      mode, e.g. on Glymur, 0 for "port a" and 1 for "port b" in
> +      x4x4 mode, and only index 0 (the single wide PHY) is valid in
> +      x8 mode.
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names
> +  - power-domains
> +  - power-domain-names
> +  - resets
> +  - reset-names
> +  - vdda-phy-supply
> +  - vdda-pll-supply
> +  - vdda-refgen0p9-supply
> +  - vdda-refgen1p2-supply
> +  - qcom,link-mode
> +  - "#clock-cells"
> +  - clock-output-names
> +  - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,glymur-gcc.h>
> +    #include <dt-bindings/clock/qcom,glymur-tcsr.h>
> +
> +    phy@f00000 {
> +      compatible = "qcom,glymur-qmp-gen5x8-pcie-phy";
> +      reg = <0x00f00000 0x10000>, <0x00f10000 0x10000>;
> +      reg-names = "port_a", "port_b";
> +
> +      clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>,
> +               <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
> +               <&tcsr TCSR_PCIE_3_CLKREF_EN>,
> +               <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>,
> +               <&gcc GCC_PCIE_3A_PIPE_CLK>,
> +               <&gcc GCC_PCIE_PHY_3B_AUX_CLK>,
> +               <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
> +               <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>,
> +               <&gcc GCC_PCIE_3B_PIPE_CLK>,
> +               <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>;
> +      clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
> +                    "phy_b_aux", "cfg_ahb_b", "rchng_b", "pipe_b",
> +                    "pipediv2_b";
> +
> +      resets = <&gcc GCC_PCIE_3A_PHY_BCR>,
> +               <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>,
> +               <&gcc GCC_PCIE_3B_PHY_BCR>,
> +               <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>;
> +      reset-names = "port_a", "port_a_nocsr", "port_b", "port_b_nocsr";
> +
> +      power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>,
> +                      <&gcc GCC_PCIE_3B_PHY_GDSC>;
> +      power-domain-names = "port_a", "port_b";
> +
> +      vdda-phy-supply = <&vreg_l3c>;
> +      vdda-pll-supply = <&vreg_l2c>;
> +
> +      vdda-refgen0p9-supply = <&vreg_l3c>;
> +      vdda-refgen1p2-supply = <&vreg_l2c>;
> +
> +      qcom,link-mode = <&tcsr 0x5000>;
> +
> +      #clock-cells = <1>;
> +      clock-output-names = "pcie3a_pipe_clk", "pcie3b_pipe_clk";
> +
> +      #phy-cells = <1>;
> +    };
> 
> -- 
> 2.34.1
> 

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