Re: [PATCH] x86/CPU/AMD: Fix Zen5 TLB sizes reporting

[Borislav Petkov]

On Thu, Aug 20, 2026 at 07:20:31PM -0700, Borislav Petkov wrote:
>  static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
>  {
> -	u32 ebx, eax, ecx, edx;
> +	u32 ebx, eax, ecx, edx, shift, tmp;
>  	u16 mask = 0xfff;
>  
>  	if (c->x86 < 0xf)
> @@ -1201,10 +1201,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
>  	if (c->extended_cpuid_level < 0x80000006)
>  		return;
>  
> +	shift = !!cpu_has(c, X86_FEATURE_L2_TLB_SIZE_X32) * 5;
> +
>  	cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
>  
> -	tlb_lld_4k = (ebx >> 16) & mask;
> -	tlb_lli_4k = ebx & mask;
> +	tlb_lld_4k = ((ebx >> 16) & mask) << shift;
> +	tlb_lli_4k = (ebx & mask) << shift;

Sashiko says:

| Could this shift operation overflow the target variables?
| The variables tlb_lld_4k and tlb_lli_4k are defined globally as u16.
| The architectural maximum raw value for the CPUID mask is 4095. When
| shifted by 5 for the new X32 encoding, this yields up to 131040, which
| exceeds the 65535 maximum capacity of a u16 variable.
| While current Zen 5 CPUs might report smaller values that fit safely,
| future CPUs returning larger raw values could be truncated.

I say, sure, let's get there first. More than 65K TLB entries - that would be
cheap TLB design when it comes to power... /eyeroll.

I'll gladly touch that bunch of u16s then.

> @@ -875,9 +875,11 @@ void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
>  
>  	cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
>  	l2size = ecx >> 16;
> +	shift = !!cpu_has(c, X86_FEATURE_L2_TLB_SIZE_X32) * 5;
>  
>  #ifdef CONFIG_X86_64
>  	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
> +	c->x86_tlbsize <<= shift;
>  #else

Sashiko says:

| Will this trigger a compiler warning on 32-bit builds?
| The shift variable is assigned unconditionally here, but its only usage
| is bounded by the CONFIG_X86_64 block just below it. On targets
| where CONFIG_X86_64 is not set, shift is written to but never read.

Sure, fixed.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette