Re: [PATCH] x86/CPU/AMD: Fix Zen5 TLB sizes reporting

[kernel test robot]

Hi Borislav,

kernel test robot noticed the following build warnings:

[auto build test WARNING on tip/x86/core]
[also build test WARNING on tip/master linus/master v7.2 next-20260821]
[cannot apply to tip/auto-latest]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Borislav-Petkov/x86-CPU-AMD-Fix-Zen5-TLB-sizes-reporting/20260820-192031
base:   tip/x86/core
patch link:    https://lore.kernel.org/r/20260821022031.946311-1-bp%40kernel.org
patch subject: [PATCH] x86/CPU/AMD: Fix Zen5 TLB sizes reporting
config: i386-allmodconfig (https://download.01.org/0day-ci/archive/20260824/202608240450.3JNf2siz-lkp@xxxxxxxxx/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260824/202608240450.3JNf2siz-lkp@xxxxxxxxx/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202608240450.3JNf2siz-lkp@xxxxxxxxx/

All warnings (new ones prefixed by >>):

   arch/x86/kernel/cpu/common.c: In function 'cpu_detect_cache_sizes':
>> arch/x86/kernel/cpu/common.c:860:55: warning: variable 'shift' set but not used [-Wunused-but-set-variable]
     860 |         unsigned int n, dummy, ebx, ecx, edx, l2size, shift;
         |                                                       ^~~~~


vim +/shift +860 arch/x86/kernel/cpu/common.c

   857	
   858	void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
   859	{
 > 860		unsigned int n, dummy, ebx, ecx, edx, l2size, shift;
   861	
   862		n = c->extended_cpuid_level;
   863	
   864		if (n >= 0x80000005) {
   865			cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
   866			c->x86_cache_size = (ecx>>24) + (edx>>24);
   867	#ifdef CONFIG_X86_64
   868			/* On K8 L1 TLB is inclusive, so don't count it */
   869			c->x86_tlbsize = 0;
   870	#endif
   871		}
   872	
   873		if (n < 0x80000006)	/* Some chips just has a large L1. */
   874			return;
   875	
   876		cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
   877		l2size = ecx >> 16;
   878		shift = !!cpu_has(c, X86_FEATURE_L2_TLB_SIZE_X32) * 5;
   879	

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