RE: [PATCH v24 10/15] mmc: renesas_sdhi: Add write32_hook for CTL_SD_CARD_CLK_CTL register writes

[Biju Das]

Hi Wolfram,

Thanks for the feedback.

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> Sent: 03 September 2026 11:30
> Subject: Re: [PATCH v24 10/15] mmc: renesas_sdhi: Add write32_hook for CTL_SD_CARD_CLK_CTL register
> writes
> 
> On Thu, Aug 20, 2026 at 06:16:40PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Add a write32_hook, analogous to the existing write16_hook, so that
> > sd_ctrl_write32() can wait for the SD bus to become idle before
> > certain 32-bit register writes.
> >
> > renesas_sdhi_write32_hook() checks whether the target register is
> > CTL_SD_CARD_CLK_CTL and, if so, waits for TMIO_STAT_SCLKDIVEN via
> > renesas_sdhi_wait_idle() before the write proceeds. Other registers
> > are unaffected. As with write16_hook, the write is skipped if the hook
> > returns a non-zero error.
> 
> While technically correct, the commit message is totally not helpful because it misses to say WHY the
> change is needed. It only says WHAT is done but I can see that. G3L exceeds the 16-bit width, this is why
> we need to change the code here. 

Oops, I will add that info into commit message.

I know you use AI to assist with commit messages but please keep a
> suspicious eye on the results.
> 
> > +	host->write32_hook = renesas_sdhi_write32_hook;
> 
> Have you checked that all SoCs handled by this driver support 32-bit access to this register?

Only RZ/G3L has bits more than 16-bits for SD_CLK_CTRL,
This patch is a preparatory patch and has no impact on other SoCs.

Cheers,
Biju