Re: [PATCH 2/4] arm64: dts: microchip: lan969x: add SDMMC nodes

[Robert Marko]

On Tue, Aug 25, 2026 at 7:14 PM Aubin Constans
<aubin.constans@xxxxxxxxxxxxx> wrote:
>
> On 24/08/2026 12:56, Robert Marko wrote:
> > Add nodes for both SDMMC controllers.
> >
> > Signed-off-by: Robert Marko <robert.marko@xxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/microchip/lan9691.dtsi | 24 ++++++++++++++++++++++
> >   1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/microchip/lan9691.dtsi b/arch/arm64/boot/dts/microchip/lan9691.dtsi
> > index a8541c6a098d..2d943ea75768 100644
> > --- a/arch/arm64/boot/dts/microchip/lan9691.dtsi
> > +++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi
> > @@ -414,6 +414,30 @@ qspi0: spi@e0804000 {
> >                          status = "disabled";
> >                  };
> >
> > +               sdmmc0: mmc@e0830000 {
> > +                       compatible = "microchip,lan9691-sdhci",
> > +                                    "microchip,sam9x60-sdhci";
> > +                       reg = <0xe0830000 0x00000300>;
> > +                       interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&clks GCK_ID_SDMMC0>, <&clks GCK_ID_SDMMC0>;
> > +                       clock-names = "hclock", "multclk";
> > +                       assigned-clocks = <&clks GCK_ID_SDMMC0>;
> > +                       assigned-clock-rates = <100000000>;
>
> If always targeting an e.MMC, capped at the High Speed DDR mode, one might consider
> a multiple of 52 MHz here.

Hi Aubin,
The issue is that LAN969x cannot derive a 52MHz nor 104Mhz clock.
Requsting 104MHz would be around 111MHz, while with 100MHz the end
clock is 50MHz.

Regards,
Robert
>
> > +                       status = "disabled";
> > +               };
> > +
> > +               sdmmc1: mmc@e0838000 {
> > +                       compatible = "microchip,lan9691-sdhci",
> > +                                    "microchip,sam9x60-sdhci";
> > +                       reg = <0xe0838000 0x00000300>;
> > +                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&clks GCK_ID_SDMMC1>, <&clks GCK_ID_SDMMC1>;
> > +                       clock-names = "hclock", "multclk";
> > +                       assigned-clocks = <&clks GCK_ID_SDMMC1>;
> > +                       assigned-clock-rates = <45000000>;
> > +                       status = "disabled";
> > +               };
> > +
> >                  qspi2: spi@e0834000 {
> >                          compatible = "microchip,lan9691-qspi";
> >                          reg = <0xe0834000 0x00000100>,
> > --
> > 2.55.0
> >
>


-- 
Robert Marko
Staff Embedded Linux Engineer
Sartura d.d.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko@xxxxxxxxxx
Web: www.sartura.hr