Re: [PATCH net 3/3] net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value

[Jakub Kicinski]

On Mon, 7 Sep 2026 18:28:32 +0200 Maxime Chevallier wrote:
> On 9/7/26 15:48, Jan Havran (Advantech Czech) wrote:
> > Per the GSW145 data sheet, the FCONTX (bits 8:7) and FCONRX (bits 6:5)
> > flow-control fields of the PHY_ADDR_n register both encode 00 = AUTO,
> > 01 = EN, 10 = reserved, 11 = DIS. GSWIP_MDIO_PHY_FCONTX_EN was 0x0100,
> > i.e. field value 10 (the reserved encoding), instead of 0x0080 (01 = EN);
> > FCONRX_EN is already 0x0020 (01). Enabling tx flow control therefore wrote
> > the reserved value.
> > 
> > Set FCONTX_EN to 0x0080. The register is shared by all supported parts.
> > 
> > Fixes: 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
> > Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@xxxxxxxx>  
> 
> Reviewed-by: Maxime Chevallier <maxime.chevallier@xxxxxxxxxxx>

Other than this last patch the series reads like net-next material 
to me TBH. New board enablement. Is that fair?

No need to repost either way.

And thanks for quick reviews!