[PATCH v3 03/13] dt-bindings: media: qcom,sm8750-iris: Add context bank subnodes
From: Vikash Garodia
Date: Wed Sep 09 2026 - 12:01:59 EST
The VPU issues DMA through several SMMU streams, and the hardware does
not give every stream the same addressable range. The non-pixel stream
cannot address the low 600MB of IOVA space, while the pixel stream can
address the full range:
+-----------------------------------------------------------+
| non-pixel stream addressable range (600 MB - 3.5 GB) |
| 0x25800000 - 0xe0000000 |
+-----------------------------------------------------------+
| pixel stream addressable range (0 - 3.5 GB) |
| 0x00000000 - 0xe0000000 |
+-----------------------------------------------------------+
A single "iommus" property on the video-codec node puts every stream in
one IOMMU domain sharing one IOVA allocator, so nothing restricts a
non-pixel buffer to avoid 0 to 600MB. Once an allocation lands below
that boundary the hardware faults, which shows up as unhandled SMMU page
faults and spontaneous reboots:
https://gitlab.freedesktop.org/drm/msm/-/work_items/100
Given that the address range restriction is for specific VPU stream, it
should be ideally be moved to that stream. To achieve the same, a subset
of streams is now represented as subnodes, so that each can be
associated with its respective addressable range. The design was discussed
and agreed by mainatiners here
https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@xxxxxxxxxx
In the past, this limitation was addressed with an iommu-map approach,
with the iris driver dynamically creating the devices. That approach
was later concluded to be a hack to avoid having subnodes, and was NAKed
by the iommu maintainers. It was discussed in detail here:
https://lore.kernel.org/all/c7b956a9-d3e8-4e18-b780-5d08f5cd2ca1@xxxxxxxxxx/
Update example to the subnode form. Doing so, it picks up the supporting
properties needed on the video-codec node, address-cells, size-cells and
dma-ranges to declare 1:1 DMA translation into the parent. Given a soc
with address-cells and size-cells as 2, update the video-codec "reg"
accordingly.
This patch depends-on:
https://github.com/devicetree-org/dt-schema/pull/207
Co-developed-by: Vishnu Reddy <busanna.reddy@xxxxxxxxxxxxxxxx>
Signed-off-by: Vishnu Reddy <busanna.reddy@xxxxxxxxxxxxxxxx>
Signed-off-by: Vikash Garodia <vikash.garodia@xxxxxxxxxxxxxxxx>
---
.../bindings/media/qcom,sm8750-iris.yaml | 187 +++++++++++----------
1 file changed, 101 insertions(+), 86 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml
index c42d3470bdac796cc878090e65becf6b62bd80ca..eafd8654092468e4422de65c12fae8606babbd32 100644
--- a/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml
@@ -72,7 +72,6 @@ required:
- dma-coherent
- interconnects
- interconnect-names
- - iommus
- power-domain-names
- resets
- reset-names
@@ -92,95 +91,111 @@ examples:
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
- video-codec@aa00000 {
- compatible = "qcom,sm8750-iris";
- reg = <0x0aa00000 0xf0000>;
-
- clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
- <&videocc_mvs0c_clk>,
- <&videocc_mvs0_clk>,
- <&gcc GCC_VIDEO_AXI1_CLK>,
- <&videocc_mvs0c_freerun_clk>,
- <&videocc_mvs0_freerun_clk>;
- clock-names = "iface",
- "core",
- "vcodec0_core",
- "iface1",
- "core_freerun",
- "vcodec0_core_freerun";
-
- dma-coherent;
- iommus = <&apps_smmu 0x1940 0>,
- <&apps_smmu 0x1947 0>;
-
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "cpu-cfg",
- "video-mem";
-
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
-
- operating-points-v2 = <&iris_opp_table>;
-
- memory-region = <&video_mem>;
-
- power-domains = <&videocc_mvs0c_gdsc>,
- <&videocc_mvs0_gdsc>,
- <&rpmhpd RPMHPD_MXC>,
- <&rpmhpd RPMHPD_MMCX>;
- power-domain-names = "venus",
- "vcodec0",
- "mxc",
- "mmcx";
-
- resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
- <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
- <&videocc_mvs0c_freerun_clk_ares>,
- <&videocc_mvs0_freerun_clk_ares>;
- reset-names = "bus0",
- "bus1",
- "core",
- "vcodec0_core";
-
- iris_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-240000000 {
- opp-hz = /bits/ 64 <240000000>;
- required-opps = <&rpmhpd_opp_low_svs_d1>,
- <&rpmhpd_opp_low_svs_d1>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ video-codec@aa00000 {
+ compatible = "qcom,sm8750-iris";
+ reg = <0x0 0x0aa00000 0x0 0xf0000>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc_mvs0c_clk>,
+ <&videocc_mvs0_clk>,
+ <&gcc GCC_VIDEO_AXI1_CLK>,
+ <&videocc_mvs0c_freerun_clk>,
+ <&videocc_mvs0_freerun_clk>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun";
+
+ dma-coherent;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ memory-region = <&video_mem>;
+
+ power-domains = <&videocc_mvs0c_gdsc>,
+ <&videocc_mvs0_gdsc>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
+ <&videocc_mvs0c_freerun_clk_ares>,
+ <&videocc_mvs0_freerun_clk_ares>;
+ reset-names = "bus0",
+ "bus1",
+ "core",
+ "vcodec0_core";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x0 0x0 0x0 0xe0000000>;
+
+ non-pixel {
+ iommus = <&apps_smmu 0x1940 0x0>;
+ iommu-ranges = <0x25800000 0xba800000>;
};
- opp-338000000 {
- opp-hz = /bits/ 64 <338000000>;
- required-opps = <&rpmhpd_opp_low_svs>,
- <&rpmhpd_opp_low_svs>;
+ pixel {
+ iommus = <&apps_smmu 0x1947 0x0>;
};
- opp-420000000 {
- opp-hz = /bits/ 64 <420000000>;
- required-opps = <&rpmhpd_opp_svs>,
- <&rpmhpd_opp_svs>;
- };
-
- opp-444000000 {
- opp-hz = /bits/ 64 <444000000>;
- required-opps = <&rpmhpd_opp_svs_l1>,
- <&rpmhpd_opp_svs_l1>;
- };
-
- opp-533333334 {
- opp-hz = /bits/ 64 <533333334>;
- required-opps = <&rpmhpd_opp_nom>,
- <&rpmhpd_opp_nom>;
- };
-
- opp-630000000 {
- opp-hz = /bits/ 64 <630000000>;
- required-opps = <&rpmhpd_opp_turbo>,
- <&rpmhpd_opp_turbo>;
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-533333334 {
+ opp-hz = /bits/ 64 <533333334>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000>;
+ required-opps = <&rpmhpd_opp_turbo>,
+ <&rpmhpd_opp_turbo>;
+ };
};
};
};
--
2.34.1