[PATCH net-next 1/7] net: dsa: mt7530: get ctrl phy addr using a function
From: Caleb James DeLisle
Date: Wed Sep 09 2026 - 12:02:09 EST
The MDIO MT7530 has 5 integrated PHYs, of these, the first PHY has
the additional registers that are used for such things as configuring
the clock configuration for the switch. The switch is typically on
MDIO address 31 and the PHYs are 0, 1, 2, 3, and 4 with 0 being the
special one. So taking the address of mdiodev (the switch) add 1 and
modulo 31 finds the first PHY.
However there are a number of MMIO based implementations of MT7530
and on these, mdiodev is NULL though they often still have a control
PHY for the purpose. Move MT753X_CTRL_PHY_ADDR to a function which
handles the NULL condition somewhat more gracefully and allows a
place for MMIO implementations to add special case handling to
provide their control PHY address.
Signed-off-by: Caleb James DeLisle <cjd@xxxxxxxx>
---
drivers/net/dsa/mt7530.c | 54 +++++++++++++++++++++-------------------
drivers/net/dsa/mt7530.h | 2 --
2 files changed, 29 insertions(+), 27 deletions(-)
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 28f94cd25b95..9a50a492e6f0 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -46,6 +46,16 @@ static const struct mt7530_mib_desc mt7530_mib[] = {
MIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, "RxArlDrop"),
};
+static int
+mt753x_ctrl_phy_addr(struct mt7530_priv *priv)
+{
+ if (WARN_ON_ONCE(!priv->mdiodev))
+ return 0;
+
+ /* Default is 1st PHY */
+ return (priv->mdiodev->addr + 1) & (PHY_MAX_ADDR - 1);
+}
+
static void
mt7530_mutex_lock(struct mt7530_priv *priv)
{
@@ -63,32 +73,30 @@ mt7530_mutex_unlock(struct mt7530_priv *priv)
static void
core_write(struct mt7530_priv *priv, u32 reg, u32 val)
{
+ int ctl_phy = mt753x_ctrl_phy_addr(priv);
struct mii_bus *bus = priv->bus;
int ret;
mt7530_mutex_lock(priv);
/* Write the desired MMD Devad */
- ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
- MII_MMD_CTRL, MDIO_MMD_VEND2);
+ ret = bus->write(bus, ctl_phy, MII_MMD_CTRL, MDIO_MMD_VEND2);
if (ret < 0)
goto err;
/* Write the desired MMD register address */
- ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
- MII_MMD_DATA, reg);
+ ret = bus->write(bus, ctl_phy, MII_MMD_DATA, reg);
if (ret < 0)
goto err;
/* Select the Function : DATA with no post increment */
- ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+ ret = bus->write(bus, ctl_phy,
MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR);
if (ret < 0)
goto err;
/* Write the data into MMD's selected register */
- ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
- MII_MMD_DATA, val);
+ ret = bus->write(bus, ctl_phy, MII_MMD_DATA, val);
err:
if (ret < 0)
dev_err(&bus->dev, "failed to write mmd register\n");
@@ -99,6 +107,7 @@ core_write(struct mt7530_priv *priv, u32 reg, u32 val)
static void
core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
{
+ int ctl_phy = mt753x_ctrl_phy_addr(priv);
struct mii_bus *bus = priv->bus;
u32 val;
int ret;
@@ -106,26 +115,23 @@ core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
mt7530_mutex_lock(priv);
/* Write the desired MMD Devad */
- ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
- MII_MMD_CTRL, MDIO_MMD_VEND2);
+ ret = bus->write(bus, ctl_phy, MII_MMD_CTRL, MDIO_MMD_VEND2);
if (ret < 0)
goto err;
/* Write the desired MMD register address */
- ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
- MII_MMD_DATA, reg);
+ ret = bus->write(bus, ctl_phy, MII_MMD_DATA, reg);
if (ret < 0)
goto err;
/* Select the Function : DATA with no post increment */
- ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+ ret = bus->write(bus, ctl_phy,
MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR);
if (ret < 0)
goto err;
/* Read the content of the MMD's selected register */
- ret = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
- MII_MMD_DATA);
+ ret = bus->read(bus, ctl_phy, MII_MMD_DATA);
if (ret < 0)
goto err;
val = ret;
@@ -133,8 +139,7 @@ core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
val &= ~mask;
val |= set;
/* Write the data into MMD's selected register */
- ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
- MII_MMD_DATA, val);
+ ret = bus->write(bus, ctl_phy, MII_MMD_DATA, val);
err:
if (ret < 0)
dev_err(&bus->dev, "failed to write mmd register\n");
@@ -2674,8 +2679,11 @@ mt7531_setup(struct dsa_switch *ds)
{
struct mt7530_priv *priv = ds->priv;
u32 val, id;
+ int ctl_phy;
int ret, i;
+ ctl_phy = mt753x_ctrl_phy_addr(priv);
+
/* Reset whole chip through gpio pin or memory-mapped registers for
* different type of hardware
*/
@@ -2743,25 +2751,21 @@ mt7531_setup(struct dsa_switch *ds)
* phy_[read,write]_mmd_indirect is called, we provide our own
* mt7531_ind_mmd_phy_[read,write] to complete this function.
*/
- ret = mt7531_ind_c45_phy_read(priv,
- MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
- MDIO_MMD_VEND2, CORE_PLL_GROUP4);
+ ret = mt7531_ind_c45_phy_read(priv, ctl_phy, MDIO_MMD_VEND2,
+ CORE_PLL_GROUP4);
if (ret < 0)
return ret;
val = ret;
val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
val &= ~MT7531_PHY_PLL_OFF;
- ret = mt7531_ind_c45_phy_write(priv,
- MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
- MDIO_MMD_VEND2, CORE_PLL_GROUP4, val);
+ ret = mt7531_ind_c45_phy_write(priv, ctl_phy, MDIO_MMD_VEND2,
+ CORE_PLL_GROUP4, val);
if (ret < 0)
return ret;
/* Disable EEE advertisement on the switch PHYs. */
- for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr);
- i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS;
- i++) {
+ for (i = ctl_phy; i < ctl_phy + MT7530_NUM_PHYS; i++) {
mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
0);
}
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index 2bbbe617b52e..3dabbc99fbbc 100644
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -747,8 +747,6 @@ enum mt7531_xtal_fsel {
#define MT7531_PHY_PLL_OFF BIT(5)
#define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
-#define MT753X_CTRL_PHY_ADDR(addr) (((addr) + 1) & (PHY_MAX_ADDR - 1))
-
#define CORE_PLL_GROUP5 0x404
#define RG_LCDDS_PCW_NCPO1_MASK GENMASK(15, 0)
#define RG_LCDDS_PCW_NCPO1(x) FIELD_PREP(RG_LCDDS_PCW_NCPO1_MASK, x)
--
2.39.5