[PATCH 31/34] arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru
Date: Thu Sep 10 2026 - 10:05:49 EST
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcieport0 and pcie1_port0, allowing board-level
overrides. Move perst-gpios/wake-gpios from the controller overrides
to the respective port nodes in the board files, renaming perst-gpios
to reset-gpios to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 14 ++++++++------
arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 14 ++++++++------
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 16 ++++++++++------
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 +++---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++++------
5 files changed, 33 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
index 668c183bc177..9fb53fd8c3f5 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
@@ -1074,9 +1074,6 @@ &mdss_dp0_out {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -1084,6 +1081,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1108,15 +1108,17 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_port0 {
/* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */
usb-controller@0 {
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index b73ad7861eb4..b0dc9f134497 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -1027,9 +1027,6 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -1037,6 +1034,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1061,15 +1061,17 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l3e_0p9>;
vdda-pll-supply = <&vreg_l3i_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index 1332c864801f..945ebe063dac 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -642,15 +642,17 @@ &mdss_dsi0_phy {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l1i_0p88>;
vdda-pll-supply = <&vreg_l3i_1p2>;
@@ -659,15 +661,17 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l3e_0p9>;
vdda-pll-supply = <&vreg_l3i_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index 2e874f046a0e..c1971638561b 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -1021,9 +1021,6 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -1031,6 +1028,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index b679fd8afb7d..39ecf4686c4b 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -3700,9 +3700,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
num-lanes = <2>;
bus-range = <0 0xff>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>,
@@ -3769,6 +3766,8 @@ pcieport0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -3893,9 +3892,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
num-lanes = <2>;
bus-range = <0 0xff>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
dma-coherent;
#address-cells = <3>;
@@ -3978,6 +3974,8 @@ pcie1_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1