Re: [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264

[Jon Hunter]

On 02/09/2026 11:17, Thierry Reding wrote:
> From: Thierry Reding <treding@xxxxxxxxxx>
>
> Use #address-cells = <1> and #size-cells = <1> because we don't need
> 64-bit register addressing for this hardware. While at it, also adjust
> the ranges property to encompass the entire AHUB range as per the TRM.
>
> Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
> ---
>   arch/arm64/boot/dts/nvidia/tegra264.dtsi | 118 +++++++++++++++----------------
>   1 file changed, 59 insertions(+), 59 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index 6b2e3a6ab810..4ed7dabafee5 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -129,13 +129,13 @@ aconnect@9000000 {
>   			power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>;
>   			status = "disabled";

...

>   					ports {
> @@ -1584,7 +1584,7 @@ sfc1_cif_out: endpoint {
>   				tegra_sfc2: sfc@9710000 {
>   					compatible = "nvidia,tegra264-sfc",
>   							"nvidia,tegra210-sfc";
> -					reg = <0x0 0x9710000 0x0 0x10000>;
> +					reg = <0x9710000 x0 0x10000>;


Looks like a typo crept in here 'x0' which is what kernelci is
complaining about [0].

Jon

[0] https://lore.kernel.org/linux-tegra/178905234343.3919.16985173968804561026@xxxxxxxxxxxx/T/#u

--
nvpublic